SpiNAPSE

This project investigates end-to-end workflows to model, train, and deploy spiking neural networks (SNNs) on FPGA-based PSoCs (programmable system-on-a-chip, including, among other components, programmable logic, i.e., an embedded FPGA) for energy-efficient, low-latency edge AI. It thereby tackles key challenges, such as immature approaches for training and data conversion, fragmented toolchains, missing benchmarks, and hardware mapping limitations, by developing a modular SNN software pipeline, designing scalable FPGA accelerators, and prototyping a proof-of-concept demonstrator. The expected outcomes include automated model-to-bitstream flows, the evaluation of speed and energy efficiency against established baselines, and a provision of design guidelines for developing hardware-accelerated SNNs.

The ultimate goal of this project, in cooperation with the Schaeffler Hub for Advanced Research at Friedrich-Alexander-Universität Erlangen-Nürnberg (SHARE at FAU), funded by Schaeffler, is to advance the modeling and training of SNNs as well as the respective design of digital hardware accelerators for SNNs to enable fast, accurate, and energy-efficient computation for the next generation of edge-AI applications, while exploring their potential and applicability, particularly across domains such as industrial automation, electric mobility, and robotics.