Entwurfsmethodik für eingebettete Systeme bestehend aus kleinen Netzwerken hardwarerekonfigurierbarer Knoten und -verbindungen

The aim of this project is the investigation of design methodologies for a novel architectural class of computer systems characterized by networking and reconfigurability at the hardware level. This architectural class of computer system are specially designed for a given technical context: embedded systems. The reconfigurability is not only limited to a node of the network, but the connection can also be reconfigurable as well. Examples of applications of such reconfigurable networks are automotive electrics and body-area-networks. Especially the trends in automotive electrics point out that more and more specialized embedded systems are linked together presenting complex systems. This stems from the fact that often there is a benefit to process sensor data locally. Therefore, we can find up to 100 processing units spread over the entire vehicle in today’s upper class cars. Meanwhile, the increasing number of processing units leads to high monetary costs. Another drawback is the requirement that a function can only be maintained as long as a sensor or actuator is connected to a proper working node. Furthermore, the computational nodes work often only at a fraction of their capacity. In addition, the nodes of the network are not designed to take over the work of faulty modules. Similar aspects are applicable in the research field for body-area-networks. In such applications, new sensors and actuators as well as new functionalities should be integrated in a running system without exchanging the hardware. In both areas we focus on the design methodology of embedded systems with the following emphasis: flexibility extendibility functional specialisation fault tolerance efficiency Doubtless, software offers the highest flexibility but is limited in performance and power efficiency. The three contradictory properties flexibility, functional specialisation and fault tolerance can all be obtained together by the use of reconfigurable networks.
Modelling: In order to better analyse the system reliability and the fault-tolerance of the system and for a better understanding of the optimizing and synthesis steps, we rely on a graph-based approach to model static applications and static architectures. With the introduction of a graph hierarchy, the model is extended in such a way that, from the application view, it becomes possible to model the time variant load of a system as selection problem of a set or a subset of all possible active processes. With the reconfigurability at different levels (network at the macro level and node at a micro level), the possibility to investigate the hierarchy is given. The configuration of a node for example is represented in such a way that a hierarchy node (cluster) could be chosen as temporal alternative. If we model sensor-, controller- und actuator-processes (a so called Sensor-Controller-Actuator-Chain) through different processes, then it is also possible to distribute those processes to different hardware nodes. The processes can be even migrated at run-time from hardware node to hardware node.
Time-invariant Allocations and Bindings: For static architectures, we define once at compile time the allocation a (which nodes should contain the best architecture for the given application), the binding b (which processes run on a given node?) and the scheduling T (when, respectively in which order and with which priority a process runs on the node to which it was allocated?). Since we consider the case where connections as well as nodes could be defect and the case where nodes or connections can be added to the system, a, b and T will be defined according to the run-time t. Therefore, we will have time parameterized allocations a, bindings b and schedulings T. If an allocated node fails at time t for example, the allocation a(t) has to be changed.
Fault tolerance and reliability analysis of ReCoNets: We consider the two following cases : the first case happens when a connection fails and the second case happens when a node fails. In the first case, the data which were using the failed connection should be routed on another path, if such a path is available in the network. Instead of a using a probabilistic approach (the so-called reliability respectively the fault probability), we try to find out here how many nodes are allowed to fail in the system at the same time? We expect to analyse and to solve this problem using the specification graph’s topology, since the reliability of a system depends on the topology of the specification graph, particularly on the binding possibilities.

Synthesis and Optimization: In order to ensure fault tolerance and thus reliability, there is no central control unit in a ReCoNet to manage the migration of processes. We use a local approach for fault detection and fault reparation when a node or a connection fails or when a node or a connection is added to the system.
Implementation: The methods for detecting faulty connections and nodes as well as the first results on rerouting and online repartitioning should be available and presented as a prototype at the end of 2004. For this purpose, a ReCoNet with four nodes is currently in implementation. A node is an Altera Excalibur board featuring an Apex FPGA with which it is possible to implement a NIOS microprocessor and additionally configure different modules like timer, UARTs, and other interfaces.