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Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs (B05)

Investigated are invasive Networks-on-Chip (iNoCs) with the goal of increasing the predictability of the execution properties of concurrent applications. Here, the hardware support inside the iNoC for mapping actor-oriented task models to a NoC is needed. Tighter bounds for communication latency shall be feasible through novel circuit switching concepts. Additionally, other non-functional properties such as security, fault tolerance, and energy consumption will be investigated. Finally, novel NoC topologies (i.e. 3D NoCs) and cache coherence are topics of investigation.

 
URL: http://invasic.informatik.uni-erlangen.de/en/tp_b5_PhII.php