CoMap › Department of Computer Science 12

Co-Design of Massively Parallel Embedded Processor Architectures

Schematische Darstellung einer Design Space Exploration

The CoMap project deals with the systematic (a) mapping, (b) evaluation, and (c) exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers.

The investigated class of computer architectures can be described by massively parallel networked processing elements which, using today's hardware technology, may be implemented on a single chip (SoC - System on a Chip).

Publikationen

Kissler D., Gran D., Salcic Z., Hannig F., Teich J.:
Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays
In: IEEE Embedded Systems Letters 3 (2011), p. 58-61
ISSN: 1943-0663
DOI: 10.1109/LES.2011.2124438
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Kissler D., Hannig F., Teich J.:
Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays
In: Journal of Low Power Electronics 7 (2011), p. 29-40
ISSN: 1546-1998
DOI: 10.1166/jolpe.2011.1114
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Vander Aa T., Raghavan P., Mahlke S., De Sutter B., Shrivastava A., Hannig F.:
Compilation Techniques for CGRAs: Exploring All Parallelization Approaches
International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'10) (Scottsdale, AZ, 24. October 2010 - 29. October 2010)
In: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis 2010
DOI: 10.1145/1878961.1878995
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Dutta H., Hannig F., Schmid M., Keinert J.:
Modeling and synthesis of communication subsystems for loop accelerator pipelines
21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. July 2010 - 9. July 2010)
In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
DOI: 10.1109/ASAP.2010.5540760
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Hannig F.:
Scheduling Techniques for High-Throughput Loop Accelerators (Dissertation, 2009)
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Dutta H., Zhai J., Hannig F., Teich J.:
Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines
20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Boston, MA, 7. July 2009 - 9. July 2009)
In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors 2009
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Keinert J., Dutta H., Hannig F., Haubelt C., Teich J.:
Model-based synthesis and optimization of static multi-rate image processing algorithms
2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (Nice, 20. April 2009 - 24. April 2009)
In: Proceedings of Design, Automation and Test in Europe (DATE 2009) 2009
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=70350072695&origin=inward
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Hannig F., Dutta H., Teich J.:
Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_5
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Dutta H., Hannig F., Teich J.:
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_23
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Kissler D., Strawetz A., Hannig F., Teich J.:
Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures
In: Journal of Low Power Electronics 5 (2009), p. 96-105
ISSN: 1546-1998
DOI: 10.1166/jolpe.2009.1008
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Kissler D., Strawetz A., Hannig F., Teich J.:
Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (Lisbon, 10. September 2008 - 12. September 2008)
In: Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2008
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Dutta H., Kissler D., Hannig F., Kupriyanov O., Teich J., Pottier B.:
A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors
In: Microprocessors and Microsystems 33 (2009), p. 53-62
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2008.08.007
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Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures
International Conference on Field Programmable Logic and Applications (FPL) (Heidelberg, 8. September 2008 - 10. September 2008)
In: Proceedings of the International Conference on Field Programmable Logic and Applications, New York: 2008
DOI: 10.1109/FPL.2008.4629969
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Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.1
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Schaffer R., Merker R., Hannig F., Teich J.:
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.24
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Kupriyanov O., Hannig F., Kissler D., Teich J.:
MAML: An ADL for Designing Single and Multiprocessor Architectures
In: Prabhat Mishra and Nikil Dutt (ed.): Processor Description Languages, Elsevier Inc., 2008, p. 295-327 (Systems on Silicon Series)
ISBN: 9780123742872
DOI: 10.1016/B978-012374287-2.50015-X
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Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (Palo Alto, CA, 14. April 2008 - 15. April 2008)
In: Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines 2008
DOI: 10.1109/FCCM.2008.16
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Hannig F., Ruckdeschel H., Teich J.:
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications
GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Freiburg, 3. March 2008 - 5. March 2008)
In: Proceedings of the GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2008
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Dutta H., Hannig F., Kupriyanov O., Kissler D., Teich J., Schaffer R., Siegel S., Merker R., Pottier B.:
Massively Parallel Processor Architectures: A Co-design Approach
3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) (Montpellier, 18. June 2007 - 20. June 2007)
In: Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) 2007
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Teich J., Hannig F., Ruckdeschel H., Dutta H., Kissler D., Stravet A.:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, 25. June 2007 - 28. June 2007)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 2007
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Dutta H., Hannig F., Ruckdeschel H., Teich J.:
Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays
In: Journal of Systems Architecture 53 (2007), p. 300-309
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2006.10.009
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Kupriyanov O., Kissler D., Hannig F., Teich J.:
Efficient event-driven simulation of parallel processor architectures
10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007 (Nice)
In: Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2007
DOI: 10.1145/1269843.1269854
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Kupriyanov O., Hannig F., Kissler D., Teich J., Lallet J., Sentieys O., Pillement S.:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures
In: Technical Report 05-2006, 2006
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Kupriyanov O., Hannig F., Kissler D., Teich J., Lallet J., Sentieys O., Pillement S.:
Modeling of interconnection networks in massively parallel processor architectures
20th International Conference on Architecture of Computing Systems, ARCS 2007 (Zurich, 12. March 2007 - 15. March 2007)
In: Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007) 2007
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=37249015485&origin=inward
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Kissler D., Kupriyanov O., Hannig F., Teich J.:
A highly parameterizable parallel processor array architecture
2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (Bangkok, 13. December 2006 - 15. December 2006)
In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006) 2006
DOI: 10.1109/FPT.2006.270293
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Kissler D., Hannig F., Kupriyanov O., Teich J.:
Hardware cost analysis for weakly programmable processor arrays
2006 International Symposium on System-on-Chip, SOC (Tampere, 14. November 2006 - 16. November 2006)
In: Proceedings of the International Symposium on System-on-Chip (SoC) 2006
DOI: 10.1109/ISSOC.2006.321996
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Hannig F., Merker R., Siegel S., Teich J.:
Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays
18th International Conference on Parallel and Distributed Computing and Systems (PDCS) (Dallas, TX, 13. November 2006 - 15. November 2006)
In: Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems 2006
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Dutta H., Hannig F., Teich J.:
Hierarchical Partitioning for Piecewise Linear Algorithms
5th International Conference on Parallel Computing in Electrical Engineering (PARELEC) (Bialystok, 13. September 2006 - 17. September 2006)
In: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering 2006
DOI: 10.1109/PARELEC.2006.43
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Dutta H., Hannig F., Heigl B., Hornegger H., Teich J.:
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Steamboat Springs, CO, 11. September 2006 - 13. September 2006)
In: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors 2006
DOI: 10.1109/ASAP.2006.4
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Kissler D., Hannig F., Kupriyanov O., Teich J.:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template
2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) (, 3. July 2006 - 5. July 2006)
In: Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) 2006
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Kissler D., Kupriyanov O., Hannig F., Koch D., Teich J.:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs
International Conference on Computer Design (CDES) (Las Vegas, NV)
In: Proceedings of the International Conference on Computer Design (CDES) 2006
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Dutta H., Hannig F., Teich J.:
Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology
In: International Journal of Embedded Systems 2 (2006), p. 114-127
ISSN: 1741-1068
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Hannig F., Dutta H., Teich J.:
Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays -- Architectural Parameters and Methodology
In: International Journal of Embedded Systems 2 (2006), p. 114-127
ISSN: 1741-1068
DOI: 10.1504/IJES.2006.010170
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Dutta H., Hannig F., Teich J.:
A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms
In: Technical Report 04-2006, 2006
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Kupriyanov O., Hannig F., Kissler D., Schaffer R., Teich J.:
MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I
In: Technical Report 03-2006, 2006
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Dutta H., Hannig F., Teich J.:
Controller Synthesis for Mapping Partitioned Programs on Array Architectures
19th International Conference on Architecture of Computing Systems (ARCS) (Frankfurt am Main, 13. March 2006 - 16. March 2006)
In: Proceedings of the 19th International Conference on Architecture of Computing Systems, Berlin, Heidelberg, New York: 2006
DOI: 10.1007/11682127_13
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Kupriyanov O., Hannig F., Kissler D., Teich J., Schaffer R., Merker R.:
An Architecture Description Language for Massively Parallel Processor Architectures
9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Dresden, 20. February 2006 - 22. February 2006)
In: Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2006
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Dutta H., Hannig F., Teich J.:
Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints
6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing (Paderborn, 17. January 2006 - 18. January 2006)
In: Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, Paderborn, Germany: 2006
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Dutta H., Hannig F., Teich J.:
Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures
In: Technical Report 03-2005, 2005
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Dutta Hritam, Hannig Frank, Ruckdeschel Holger, Teich Jürgen:
Automatic FIR Filter Generation for FPGAs
Embedded Computer Systems: Architectures, Modeling, and Simulation. (Island of Samos, 18. July 2005 - 20. July 2005)
In: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), Berlin, Heidelberg, New York: 2005
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Hannig F., Teich J.:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. June 2005 - 30. June 2005)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
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Dutta H., Hannig F., Kupriyanov O., Teich J., Schaffer R., Siegel S., Merker R., Keryell R., Pottier B., Chillet D., Ménard D., Sentieys O.:
Co-Design of Massively Parallel Embedded Processor Architectures
First ReCoSoC Workshop (Montpellier)
In: Proceedings of the first ReCoSoC Workshop 2005
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Hannig F., Teich J.:
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP ) (Galveston, TX, 27. September 2004 - 29. September 2004)
In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2004) 2004
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Hannig F., Teich J.:
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms
In: Technical Report 01-2004, 2004
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Hannig F., Teich J.:
Dynamic Piecewise Linear/Regular Algorithms
Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ) (Dresden, 7. September 2004 - 10. September 2004)
In: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) 2004
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Hannig F., Dutta H., Teich J.:
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology
18th International Parallel and Distributed Processing Symposium (IPDPS 2004), (Santa Fe, NM, 26. April 2004 - 30. April 2004)
In: Proceedings of the 18th International Parallel and Distributed Processing Symposium 2004
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Hannig F., Dutta H., Teich J.:
Regular Mapping for Coarse-grained Reconfigurable Architectures
IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ) (Montreal, Quebec, 17. May 2004 - 21. May 2004)
In: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing 2004
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