Publications

Our publications

Esper K., Wildermann S., Teich J.:
Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs
30th Asia and South Pacific Design Automation Conference ASP-DAC 2025 (Tokyo, 20. January 2025 - 23. January 2025)
BibTeX: Download
Spieck J., Walter D., Waschkeit J., Teich J.:
Co-Design of Sustainable Embedded Systems-on-Chip
Design, Automation and Test in Europe Conference 2025 (Lyon, 31. March 2025 - 2. April 2025)
In: Design, Automation and Test in Europe Conference 2025
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Bassimir B., Wanka R.:
On the Computation of Robust Examination Timetables: Methods and Experimental Results
In: Journal of Scheduling (2024)
ISSN: 1094-6136
DOI: 10.1007/s10951-024-00815-y
BibTeX: Download
Deutel M., Hannig F., Mutschler C., Teich J.:
Fused-Layer CNNs for Memory-Efficient Inference on Microcontrollers
Workshop on Machine Learning and Compression @ NeurIPS 2024 (Vancouver Convention Center, 10. December 2024 - 15. December 2024)
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Deutel M., Hannig F., Mutschler C., Teich J.:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)
ISSN: 0278-0070
DOI: 10.1109/TCAD.2024.3484354
URL: https://ieeexplore.ieee.org/document/10726519
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Esper K., Teich J.:
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024) (Munich, 17. January 2024 - 19. January 2024)
In: Patrick Meumeu Yomsi, Stefan Wildermann (ed.): Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024), Saarbrücken/Wadern: 2024
DOI: 10.4230/OASIcs.NG-RES.2024.4
URL: https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.4
BibTeX: Download
Esper K., Wildermann S., Teich J.:
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs
Design, Automation and Test in Europe Conference (Valencia, 25. March 2024 - 27. March 2024)
URL: https://ieeexplore.ieee.org/document/10546881
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Groth S., Schmid M., Teich J., Hannig F.:
Estimating the Execution Time of CNN Inference on GPUs
27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. February 2024 - 15. February 2024)
In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
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Hahn T., Schüll D., Wildermann S., Teich J.:
ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (Kielce, 3. April 2024 - 5. April 2024)
In: IEEE Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems 2024
DOI: 10.1109/DDECS60919.2024.10508904
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Hahn T., Wildermann S., Teich J.:
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Turin, 2. September 2024 - 6. September 2024)
In: IEEE Proceedings of the 34th International Conference on Field-Programmable Logic and Applications 2024
DOI: 10.1109/FPL64840.2024.00012
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Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers
10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Angers, 2. May 2024 - 4. May 2024)
DOI: 10.5220/0000186800003702
BibTeX: Download
Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
In: The Computing Research Repository (CoRR), 2024
DOI: 10.48550/arXiv.2404.15833
URL: https://arxiv.org/abs/2404.15833
BibTeX: Download
(online publication)
Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
2024 Stuttgart International Symposium on Automotive and Engine Technology (Stuttgart, 2. July 2024 - 3. July 2024)
In: André Casal Kulzer, Hans-Christian Reuss, Andreas Wagner (ed.): Proceeding of the 2024 Stuttgart International Symposium on Automotive and Engine Technology, Wiesbaden: 2024
DOI: 10.1007/978-3-658-45018-2_4
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Heidorn C., Sabih M., Meyerhöfer N., Schinabeck C., Teich J., Hannig F.:
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks
In: International Journal of Parallel Programming 52 (2024), p. 40 - 58
ISSN: 0885-7458
DOI: 10.1007/s10766-024-00760-5
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Jungnitz N., Keszöcze O.:
SAS - A Framework for Symmetry-based Approximate Synthesis
Design Automation Conference (San Francisco, 23. June 2024 - 27. June 2024)
DOI: 10.1145/3649329.3658495
BibTeX: Download
Karim A., Falk J., Schmidt D., Teich J.:
Self-Powering Dataflow Networks – Concepts and Implementation
22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) (Raleigh, NC, 3. October 2024 - 4. October 2024)
DOI: 10.1109/MEMOCODE63347.2024.00013
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Kergaßner M., Keszöcze O., Wanka R.:
Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes
Genetic and Evolutionary Computation Conference (GECCO) (Melbourne, 14. July 2024 - 18. July 2024)
DOI: 10.1145/3638529.3654022
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Krüger P., Wildermann S., Teich J.:
CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets
17th European Workshop on Systems Security (EuroSec) (Athen, 22. April 2024 - 22. April 2024)
In: Association for Computing Machinery (ACM) (ed.): EUROSEC '24: Proceedings of the 17th European Workshop on System Security 2024
DOI: 10.1145/3642974.3652286
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Lamberti P., Esper K., Spieck J., Velasco-Guillen RJ., Beckerle P., Teich J.:
Enforcing Safety Requirements of a Knee Orthosis Using Finite State Machines
Integrated Systems in Medical Technologies (ISMT) (Erlangen, 25. September 2024 - 26. September 2024)
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Letras M.:
Techniques for Efficient Performance Analysis and Memory Optimization in Mapping Dataflow Models of Computation onto Embedded Systems (Dissertation, 2024)
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Letras M., Falk J., Teich J.:
Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems
In: IEEE Access 12 (2024), p. 39748-39769
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2024.3375079
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Letras M., Morales-Reyes A., Cumplido R., Martínez-Peñaloza MG., Feregrino-Uribe C.:
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms
In: Microprocessors and Microsystems 104 (2024), Article No.: 104986
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2023.104986
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Meumeu Yomsi P., Wildermann S. (ed.):
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)
2024
(Open Access Series in Informatics (OASIcs), Vol. 117)
ISBN: 978-3-95977-313-3
Open Access: https://www.dagstuhl.de/dagpub/978-3-95977-313-3
URL: https://www.dagstuhl.de/dagpub/978-3-95977-313-3
BibTeX: Download
Plagwitz P., Hannig F., Teich J., Keszöcze O.:
Compiler-based Processor Network Generation for Neural Networks on FPGAs
27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. February 2024 - 15. February 2024)
In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
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Plagwitz P., Hannig F., Teich J., Keszöcze O.:
DSL-based SNN Accelerator Design using Chisel
27th Euromicro Conference Series on Digital System Design (DSD) (Paris, 27. August 2024 - 30. August 2024)
In: 2024 27th Euromicro Conference on Digital System Design (DSD) 2024
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Plagwitz P., Hannig F., Teich J., Keszöcze O.:
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation
20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) (Aveiro, 20. March 2024 - 22. March 2024)
In: Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) 2024
DOI: 10.1007/978-3-031-55673-9_1
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Sabih M., Karim A., Wittmann J., Hannig F., Teich J.:
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
International Conference on Field Programmable Technology (FPT 2024) (Sydney, Australia, 10. December 2024 - 12. December 2024)
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Sabih M., Sesli B., Hannig F., Teich J.:
Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units
Conference on Design, Automation and Test in Europe (DATE) (Valencia, 25. March 2024 - 27. March 2024)
In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2024
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Sixdenier PL., Reinhold L., Piotrowski K.:
The Base Station
In: Weather stations for biodiversity: a comprehensive approach to an automated and modular monitoring system, Advanced Books, 2024, p. 189-203
ISBN: 9786192481230
DOI: 10.3897/ab.e119534
BibTeX: Download
Sixdenier PL., Wildermann S., Teich J.:
GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation
Cyber-Physical Systems & Internet of Things 2024 (CPS&IoT'2024) (Budva, Montenegro, 11. June 2024 - 14. June 2024)
In: Proceedings of the 13th Mediterranean Conference on Embedded Computing (MECO) 2024
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Spieck J., Wildermann S., Teich J.:
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs
In: ACM Transactions on Design Automation of Electronic Systems (2024)
ISSN: 1084-4309
DOI: 10.1145/3660633
BibTeX: Download
Walter D., Adamtschuk T., Hannig F., Teich J.:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays
35th IEEE International Conference on Application-specific Systems, Architectures and Processors (Hong Kong, 24. July 2024 - 26. July 2024)
In: Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024
DOI: 10.1109/ASAP61560.2024.00029
URL: https://ieeexplore.ieee.org/document/10631126
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Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
ALPACA: An Accelerator Chip for Nested Loop Programs
IEEE International Symposium on Circuits and Systems (ISCAS) (Singapore, 19. May 2024 - 22. May 2024)
In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2024
DOI: 10.1109/ISCAS58744.2024.10558549
URL: https://ieeexplore.ieee.org/document/10558549
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Wilbert N., Wildermann S., Teich J.:
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study (Conference contribution, accepted)
10th International Symposium on Memory Systems (Washington, D.C., 30. September 2024 - 3. October 2024)
DOI: 10.1145/3695794.3695819
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Wilbert N., Wildermann S., Teich J.:
To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches
2nd Workshop on Disruptive Memory Systems (Austin, TX, 3. November 2024 - 3. November 2024)
In: Proceedings of the 2nd Workshop on Disruptive Memory Systems 2024
DOI: 10.1145/3698783.3699381
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Witt N., Deutel M., Sobel C., Schubert J., Woller P.:
Energy-Efficient AI on the Edge
In: Christopher Mutschler, Christian Münzenmayer, Norman Uhlmann, Alexander Martin (ed.): Unlocking Artificial Intelligence: From Theory to Applications, Springer Link, 2024, p. 359 - 380
DOI: 10.1007/978-3-031-64832-8_19
BibTeX: Download
Yomsi PM., Wildermann S. (ed.):
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)
Wadern: 2024
(OpenAccess Series in Informatics (OASIcs), Vol. 117)
ISBN: 9783959773133
DOI: 10.4230/OASIcs.NG-RES.2024.0
BibTeX: Download

Bartunik M., Kirchner J., Keszöcze O.:
Artificial Intelligence for Molecular Communication
In: it - Information Technology (2023)
ISSN: 1611-2776
DOI: 10.1515/itit-2023-0029
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Bosio A., Barbareschi M., Savino A., Han J., Teich J.:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems
In: IEEE Design & Test 40 (2023), p. 5-7
ISSN: 2168-2356
DOI: 10.1109/MDAT.2022.3221909
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Brand P.:
Reduction of Mobile Device Modem Energy via Adapative and Power-efficient Hybrid Online/Offline Grant Prediction for the Protocol Standards LTE and 5G (Dissertation, 2023)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-233190
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Deutel M., Mutschler C., Teich J.:
microYOLO: Towards Single-Shot Object Detection on Microcontrollers
4th Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM) (Torino, 18. September 2023 - 22. September 2023)
Open Access: https://arxiv.org/abs/2408.15865
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Deutel M., Woller P., Mutschler C., Teich J.:
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen MBMV’23 (Freiburg, 23. March 2023 - 24. March 2023)
In: VDE (ed.): MBMV 2023; 26th Workshop 2023
Open Access: https://arxiv.org/abs/2205.10369
URL: https://ieeexplore.ieee.org/document/10173060
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Esper K., Spieck J., Sixdenier PL., Wildermann S., Teich J.:
RAVEN: Reinforcement Learning for Generating Verifiable Run-time Requirement Enforcers for MPSoCs
Workshop on Next Generation Real-Time Embedded Systems Co-located with HiPEAC 2023 (Toulouse, 18. January 2023 - 18. January 2023)
In: Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023), Dagstuhl, Germany: 2023
DOI: 10.4230/OASIcs.NG-RES.2023.7
URL: https://drops.dagstuhl.de/opus/volltexte/2023/17738
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Esper K., Wildermann S., Teich J.:
Automatic Synthesis of FSMs for Enforcing Non-Functional Requirements on MPSoCs Using Multi-Objective Evolutionary Algorithms
In: ACM Transactions on Design Automation of Electronic Systems 28 (2023), p. 1-20
ISSN: 1084-4309
DOI: 10.1145/3617832
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Hahn T., Schüll D., Wildermann S., Teich J.:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing
2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) (Dresden, 6. March 2023 - 10. March 2023)
In: Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) 2023
DOI: 10.18420/BTW2023-46
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Hahn T., Wildermann S., Teich J.:
SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Göteborg, 4. September 2023 - 8. September 2023)
In: IEEE Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications 2023
DOI: 10.1109/FPL60245.2023.00034
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Heil A., Keszöcze O.:
Fast Approximate AIG-Based Synthesis
In: Rolf Drechsler, Sebastian Huhn (ed.): Advanced Boolean Techniques, Springer, 2023, p. 17 -- 32
ISBN: 978-3-031-28915-6
DOI: 10.1007/978-3-031-28916-3
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Henkel J., Sidduh L., Bauer L., Teich J., Wildermann S., Tahoori MB., Mayahinia M., Castrillon J., Khan AA., Farzaneh H., de Lima JPC., Chen JJ., Hakert C., Chen KH., Yang CL., Cheng HY.:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications
International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) (HAMBURG, 18. September 2023 - 20. September 2023)
In: Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) 2023
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Letras M., Falk J., Teich J.:
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers
Fourth Workshop on Next Generation Real-Time Embedded Systems (Toulouse, 18. January 2023 - 18. January 2023)
In: Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023), Germany: 2023
DOI: 10.4230/OASIcs.NG-RES.2023.6
URL: https://drops.dagstuhl.de/opus/volltexte/2023/17737/
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Plagwitz P., Hannig F., Teich J., Keszöcze O.:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations
(2023)
Open Access: https://arxiv.org/abs/2306.12742
URL: https://arxiv.org/abs/2306.12742
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(online publication)
Pradhan C., Letras M., Teich J.:
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation
In: ACM Transactions on Embedded Computing Systems 22 (2023), p. 1-24
ISSN: 1539-9087
DOI: 10.1145/3580737
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Sabih M., Yayla M., Hannig F., Teich J., Chen JJ.:
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods
EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and Systems (Rome, Italy, 8. May 2023 - 8. May 2023)
In: Eiko Yoneki, Luigi Nardi (ed.): EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and System, New York(NY) United States: 2023
DOI: 10.1145/3578356.3592595
URL: https://dl.acm.org/doi/10.1145/3578356.3592595
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Sixdenier PL., Wildermann S., Ottens M., Teich J.:
Seque: Lean and Energy-aware Data Management for IoT Gateways
IEEE International Conference on Edge Computing and Communications (EDGE) (Chicago, Illinois USA, 2. July 2023 - 8. July 2023)
DOI: 10.1109/EDGE60047.2023.00030
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Spieck J., Sixdenier PL., Esper K., Wildermann S., Teich J.:
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers
21st ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) (Hamburg, 21. September 2023 - 23. September 2023)
In: 2023 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) 2023
DOI: 10.1145/3610579.3611091
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Spieck J., Wildermann S., Teich J.:
A Learning-Based Methodology for Scenario-Aware Mapping of Soft Real-Time Applications onto Heterogeneous MPSoCs
In: ACM Transactions on Design Automation of Electronic Systems 28 (2023), p. 4:1 - 4:40
ISSN: 1084-4309
DOI: 10.1145/3529230
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Trautmann J.:
Automation Approaches for the Application of Side-Channel Analysis in Real-World Scenarios (Dissertation, 2023)
URL: https://open.fau.de/items/e894c57d-0839-4677-8614-ab7ac59edc91
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Trautmann J., Krüger P., Becher A., Wildermann S., Teich J.:
Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s
In: ACM Transactions on Reconfigurable Technology and Systems (2023), p. 1-27
ISSN: 1936-7406
DOI: 10.1145/3635719
URL: https://dl.acm.org/doi/10.1145/3635719
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Urfei J., Smirnov F., Weichslgartner A., Wildermann S.:
Gradient-Free Adversarial Attacks on 3D Point Clouds from LiDAR Sensors
In: Springer International Publishing (ed.): Machine Learning and Optimization Techniques for Automotive Cyber-Physical Systems, 2023, p. 225 - 256
ISBN: 978-3-031-28015-3
DOI: 10.1007/978-3-031-28016-0_7
URL: https://link.springer.com/chapter/10.1007/978-3-031-28016-0_7
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Özkan MA.:
Declarative Programming Techniques for Hardware Synthesis of Image Processing Applications (Dissertation, 2023)
BibTeX: Download

Anantharajaiah N., Asfour T., Bader M., Bauer L., Becker J., Bischof S., Brand M., Bungartz HJ., Eichler C., Esper K., Falk J., Fasfous N., Freiling F., Fried A., Gerndt M., Glaß M., Gonzalez J., Hannig F., Heidorn C., Henkel J., Herkersdorf A., Herzog B., John J., Hönig T., Hundhausen F., Khdr H., Langer T., Lenke O., Lesniak F., Lindermayr A., Listl A., Maier S., Megow N., Mettler M., Müller-Gritschneder D., Nassar H., Paus F., Pöppl A., Pourmohseni B., Rabenstein J., Raffeck P., Rapp M., Rivas SN., Sagi M., Schirrmacher F., Schlichtmann U., Schmaus F., Schröder-Preikschat W., Schwarzer T., Sikal MB., Simon B., Snelting G., Spieck J., Srivatsa A., Stechele W., Teich J., Comprés Ureña IA., Verbauwhede I., Walter D., Wild T., Wildermann S., Wille M., Witterauf M., Zhang L.:
Invasive Computing
FAU University Press, 2022
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Bader M., Wildermann S., Glaß M., Pöppl A., Pourmohseni B., Schwarzer T., Spieck J., Wille M.:
Characterisation and Analysis of Invasive Algorithmic Patterns
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 97-122
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Bartunik M., Keszöcze O., Schiller B., Kirchner J.:
Deep Learning to Demodulate Transmissions in Molecular Communication
6th Workshop on Molecular Communications (Warwick, 13. July 2022 - 15. July 2022)
In: Proceedings of the 6th Workshop on Molecular Communications 2022
DOI: 10.1109/ismict56646.2022.9828263
URL: https://molecularcommunications.org/wp-content/uploads/2022/07/Deep-Learning-to-Demodulate-Transmission-in-Molecular-Communication.pdf
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Bartunik M., Keszöcze O., Schiller B., Kirchner J.:
Using Deep Learning to Demodulate Transmissions in Molecular Communication
2022 IEEE 16th International Symposium on Medical Information and Communication Technology (ISMICT) (Online, 2. May 2022 - 4. May 2022)
DOI: 10.1109/ISMICT56646.2022.9828263
URL: https://ieeexplore.ieee.org/document/9828263
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Becher A.:
Near-Data Query Processing on Heterogeneous FPGA-based Systems (Dissertation, 2022)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-189289
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Becker J., Hannig F., Wild T., Brand M., Lenke O., Lesniak F.:
Validation and Demonstrator
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 411-431
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Brand P., Hackenberg B., Falk J., Teich J.:
Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption
International Wireless Communications and Mobile Computing Conference (IWCMC 2022) (Dubrovnik)
DOI: 10.1109/iwcmc55113.2022.9824349
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Bustio-Martinez L., Cumplido R., Letras M., Hernandez-Leon R., Feregrino-Uribe C., Hernandez-Palancar J.:
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review
In: ACM Computing Surveys 54 (2022)
ISSN: 0360-0300
DOI: 10.1145/3472289
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Echavarria Gutiérrez JA.:
On the Approximation of Arithmetic Functions and Logic Snythesis of Approximate Very Large Boolean Networks (Dissertation, 2022)
URL: https://opus4.kobv.de/opus4-fau/files/20100/DissertationJorgeEchavarria.pdf
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Echavarria Gutiérrez JA., Keszöcze O., Teich J.:
Probability-based DSE of Approximated LUT-based FPGA Designs
15th IEEE Dallas Circuits and Systems Conference (Dallas, 17. June 2022 - 19. June 2022)
DOI: 10.1109/dcas53974.2022.9845591
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Echavarria Gutiérrez JA., Wildermann S., Keszöcze O., Khosravi F., Becher A., Teich J.:
Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
In: it - Information Technology (2022)
ISSN: 1611-2776
DOI: 10.1515/itit-2021-0040
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Esper K., Wildermann S., Teich J.:
Multi-requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study
Workshop on Next Generation Real-Time Embedded Systems (NG-RES) (Budapest, 22. June 2022 - 22. June 2022)
In: Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), Dagstuhl, Germany: 2022
DOI: 10.4230/OASIcs.NG-RES.2022.2
URL: https://drops.dagstuhl.de/opus/volltexte/2022/16110/
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Friedemann A., Keszöcze O.:
Towards Clause Learning a la Carte through VarMonads
International Symposium on Logic-based Program Synthesis and Transformation (Tbilisi, 21. September 2022 - 23. September 2022)
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Hahn T., Becher A., Wildermann S., Teich J.:
Raw Filtering of JSON data on FPGAs
Design, Automation and Test in Europe Conference (DATE) (Antwerpen, 14. March 2022 - 23. March 2022)
In: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe 2022
DOI: 10.23919/DATE54114.2022.9774696
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Hahn T., Wildermann S., Teich J.:
Auto-Tuning of Raw Filters for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00036
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Hannig F., Derrien S.:
Special Issue on Applied Reconfigurable Computing
In: Journal of Signal Processing Systems (2022)
ISSN: 1939-8018
DOI: 10.1007/s11265-022-01806-y
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Heidorn C., Meyerhöfer N., Schinabeck C., Hannig F., Teich J.:
Hardware-Aware Evolutionary Filter Pruning
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. July 2022 - 7. July 2022)
DOI: 10.1007/978-3-031-15074-6_18
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Heil A., Keszöcze O.:
Fast Approximate AIG-Based Synthesis
International Workshop on Boolean Problems (Bremen, 22. September 2022 - 23. September 2022)
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Keszöcze O.:
Approximate Computing
In: it - Information Technology (2022)
ISSN: 1611-2776
DOI: 10.1515/itit-2022-0027
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Keszöcze O.:
BDD-based Error Metric Analysis, Computation and Optimization
In: IEEE Access 10 (2022), p. 14013 - 14028
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2022.3140557
URL: https://ieeexplore.ieee.org/abstract/document/9669272
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Keszöcze O.:
Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview
In: IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2022), p. 2661 - 2666
ISSN: 1057-7130
DOI: 10.1109/TCSII.2022.3173753
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Mishra A., Hannig F., Teich J., Sabih M.:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks
The 13th International Green and Sustainable Computing Conference (IGSC) (Virtual, 24. October 2022 - 27. October 2022)
In: IEEE (ed.): 2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC), Pittsburgh, PA, USA: 2022
DOI: 10.1109/IGSC55832.2022.9969363
URL: https://ieeexplore.ieee.org/document/9969374
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Plagwitz P., Hannig F., Teich J.:
TRAC: Compilation-based Design of Transformer Accelerators for FPGAs
International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00015
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Pourmohseni B., Wildermann S., Smirnov F., Meyer P., Teich J.:
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems
In: IEEE Access (2022)
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2022.3162617
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Sabih M., Hannig F., Teich J.:
DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks
2nd European Workshop on Machine Learning and Systems (EuroMLSys) (Rennes, France, 5. April 2022 - 8. April 2022)
In: Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys), New York, NY, United States: 2022
DOI: 10.1145/3517207.3526982
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Sixdenier PL., Wildermann S., Ziegler D., Teich J.:
SIDAM: A Design Space Exploration Framework for Multi-Sensor Embedded Systems Powered by Energy Harvesting
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. July 2022 - 7. July 2022)
In: Springer, Cham (ed.): International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), Switzerland: 2022
DOI: 10.1007/978-3-031-15074-6
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Snelting G., Teich J., Fried A., Hannig F., Witterauf M.:
Compilation and Code Generation for Invasive Programs
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 309-333
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Sommer J., Özkan MA., Keszöcze O., Teich J.:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks
International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00035
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Sommer J., Özkan MA., Keszöcze O., Teich J.:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 (2022), p. 3767 - 3778
ISSN: 0278-0070
DOI: 10.1109/TCAD.2022.3197512
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Sommer J., Özkan MA., Keszöcze O., Teich J.:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Shanghai, 7. October 2022 - 14. October 2022)
DOI: 10.1109/tcad.2022.3197512
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Spieck J., Wildermann S., Teich J.:
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures
CODES+ISSS 2022 (Shanghai, 10. October 2022 - 12. October 2022)
In: CODES+ISSS 2022 2022
DOI: 10.1109/TCAD.2022.3197527
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Streit FJ.:
Techniques to Secure HW/SW-Programmable SoC Architectures for Edge Computing (Dissertation, 2022)
URL: https://opus4.kobv.de/opus4-fau/files/21375/dissertation_streit_final.pdf
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Teich J., Brand M., Hannig F., Heidorn C., Walter D., Witterauf M.:
Invasive Tightly-Coupled Processor Arrays
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 177-202
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Teich J., Esper K., Falk J., Pourmohseni B., Schwarzer T., Wildermann S.:
Basics of Invasive Computing
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 69-95
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Teich J., Henkel J., Herkersdorf A.:
Introduction to Invasive Computing
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 1-66
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
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Trautmann J., Beckers A., Wouters L., Gierlichs B., Wildermann S., Verbauwhede I., Teich J.:
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces
CHES 2022 (Leuven, Belgium, 18. September 2022 - 21. September 2022)
In: IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2022
DOI: 10.46586/tches.v2022.i1.345-366
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Trautmann J., Patsiatzis N., Becher A., Teich J., Wildermann S.:
Real-Time Waveform Matching with a Digitizer at 10 GS/s
International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00025
URL: https://ieeexplore.ieee.org/document/10035208
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Trautmann J., Patsiatzis N., Becher A., Wildermann S., Teich J.:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA
ASHES 2022 (Los Angeles, CA, USA, 11. November 2022 - 11. November 2022)
In: Association for Computing Machinery (ed.): Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security 2022
DOI: 10.1145/3560834.3563828
URL: https://dl.acm.org/doi/10.1145/3560834.3563828
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Trautmann J., Teich J., Wildermann S.:
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks
30th IEEE International Symposium on Field-Programmable Custom Computing Machines (New York City, 15. May 2022 - 18. May 2022)
In: 30th IEEE International Symposium on Field-Programmable Custom Computing Machines 2022
DOI: 10.1109/FCCM53951.2022.9786190
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Wägele JW., Bodesheim P., Bourlat SJ., Denzler J., Diepenbroek M., Fonseca V., Frommolt KH., Geiger MF., Gemeinholzer B., Glöckner FO., Haucke T., Kirse A., Kölpin A., Kostadinov I., Kühl HS., Kurth F., Lasseck M., Liedke S., Losch F., Müller S., Petrovskaya N., Piotrowski K., Radig B., Scherber C., Schoppmann L., Schulz J., Steinhage V., Tschan GF., Vautz W., Velotto D., Weigend M., Wildermann S.:
Towards a multisensor station for automated biodiversity monitoring
In: Basic and Applied Ecology 59 (2022), p. 105-138
ISSN: 1439-1791
DOI: 10.1016/j.baae.2022.01.003
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Ah Sue J.:
Supervised Learning Grant Prediction for Cellular Mobile Device Power Savings (Dissertation, 2021)
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Alhaddad S., Förstner J., Groth S., Grünewald D., Grynko Y., Hannig F., Kenter T., Pfreundt FJ., Plessl C., Schotte M., Steinke T., Teich J., Weiser M., Wende F.:
HighPerMeshes -- A Domain-Specific Language for Numerical Algorithms on Unstructured Grids
18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) (Warsaw, 24. August 2020 - 24. August 2020)
In: Proceedings of the 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2020: Parallel Processing Workshops 2021
DOI: 10.1007/978-3-030-71593-9_15
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Alhaddad S., Förstner J., Groth S., Grünewald D., Grynko Y., Hannig F., Kenter T., Pfreundt FJ., Plessl C., Schotte M., Steinke T., Teich J., Weiser M., Wende F.:
The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids
In: Concurrency and Computation-Practice & Experience (2021)
ISSN: 1532-0626
DOI: 10.1002/cpe.6616
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Beena Gopalakrishnan Nair L., Becher A., Wildermann S., Meyer-Wegener K., Teich J.:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System
In: Datenbank-Spektrum (2021)
ISSN: 1618-2162
DOI: 10.1007/s13222-020-00363-7
URL: https://rd.springer.com/article/10.1007/s13222-020-00363-7
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Bosio A., O'Connor I., Traiola M., Echavarria Gutiérrez JA., Teich J., Abdullah Hanif M., Shafique M., Hamdioui S., Deveautour B., Girard P., Virazel A., Bertels K.:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*
IEEE European Test Symposium (ETS) (Virtual Conference, 24. May 2021 - 28. May 2021)
In: Proceedings of the 26th IEEE European Test Symposium (ETS) 2021
DOI: 10.1109/ETS50041.2021.9465409
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Brand P., Falk J., Ah Sue J., Brendel J., Hasholzner R., Teich J.:
Adaptive Predictive Power Management for Mobile LTE Devices
In: IEEE Transactions on Mobile Computing 20 (2021), p. 2518-2535
ISSN: 1536-1233
DOI: 10.1109/TMC.2020.2988651
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Brand P., Falk J., Maier T., Teich J.:
Simulating Realistic IoT Network Traffic Using Similarity-based DSE
International Conference on Computational Science and Computational Intelligence (CSCI) (Las Vegas, NV)
In: 2021 International Conference on Computational Science and Computational Intelligence (CSCI), New York: 2021
DOI: 10.1109/CSCI54926.2021.00276
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Brand P., Falk J., Potwigin E., Teich J.:
Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems
2021 International Symposium on Networks, Computers and Communications (ISNCC 2021) (Canadian University, Citywalk, Dubai, 31. October 2021 - 2. November 2021)
In: IEEE (ed.): Proceedings of the 2021 International Symposium on Networks, Computers and Communications (ISNCC 2021) 2021
DOI: 10.1109/ISNCC52172.2021.9615819
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Derrien S., Hannig F., Diniz PC., Chillet D.:
Applied Reconfigurable Computing. Architectures, Tools, and Applications
17th International Symposium on Applied Reconfigurable Computing 2021 (Virtual Event, 29. June 2021 - 30. June 2021)
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications 2021
DOI: 10.1007/978-3-030-79025-7
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Echavarria Gutiérrez JA., Wildermann S., Keszöcze O., Khosravi F., Becher A., Teich J.:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
(2021)
URL: http://arxiv.org/abs/2105.05588
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(online publication)
Echavarria Gutiérrez JA., Wildermann S., Teich J.:
Approximate Logic Synthesis of Very Large Boolean Networks
Design, Automation and Test in Europe, DATE 2021, February 1-5, 2021 (Alpexpo, Grenoble, 1. February 2021 - 5. February 2021)
In: Design, Automation and Test in Europe, DATE 2021 2021
DOI: 10.23919/date51398.2021.9473952
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Esper K., Wildermann S., Teich J.:
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems
Workshop on Next Generation Real-Time Embedded Systems (NG-RES) (Budapest, 20. January 2021 - 20. January 2021)
In: Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), OASICS Vol. 87 2021
DOI: 10.4230/OASIcs.NG-RES.2021.1
URL: https://drops.dagstuhl.de/opus/volltexte/2021/13477
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Esper K., Wildermann S., Teich J.:
Enforcement FSMs - Specification and Verification of Non-Functional Properties of Program Executions on MPSoCs
19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE'21) (Beijing, 20. November 2021 - 22. November 2021)
In: Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, New York, NY, USA: 2021
DOI: 10.1145/3487212.3487348
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Groth S., Teich J., Hannig F.:
Efficient Application of Tensor Core Units for Convolving Images
24th International Workshop on Software and Compilers for Embedded Systems (Eindhoven (NL), 1. November 2021 - 2. November 2021)
In: Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems 2021
DOI: 10.1145/3493229.3493305
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Guillouët Y., Keszöcze O., Sill Torres F.:
Extensive resilience analysis of function models of complex systems
Resilience Week (Washington, DC, 18. October 2021 - 21. October 2021)
DOI: 10.1109/rws52686.2021.9611802
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Hannig F., Koch D.:
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors
In: Journal of Signal Processing Systems (2021)
ISSN: 1939-8018
DOI: 10.1007/s11265-021-01708-5
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Hannig F., Meloni P., Spallanzani M., Ziegler M. (ed.):
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021)
2021
Open Access: http://arxiv.org/html/2102.00818
URL: http://arxiv.org/abs/2102.00818
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Hannig F., Teich J.:
Open Source Hardware
In: IEEE Computer 54 (2021), p. 111-115
ISSN: 0018-9162
DOI: 10.1109/MC.2021.3099046
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Heidorn C., Walter D., Candir YE., Hannig F., Teich J.:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
31st International Conference on Field Programmable Logic and Applications (FPL) (Virtual Conference, 30. August 2021 - 3. September 2021)
In: Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL) 2021
DOI: 10.1109/FPL53798.2021.00079
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Keszöcze O., Brand M., Witterauf M., Heidorn C., Teich J.:
Aarith: An Arbitrary Precision Number Library
ACM/SIGAPP Symposium On Applied Computing (virtual conference, 22. March 2021 - 26. March 2021)
DOI: 10.1145/3412841.3442085
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Keszöcze O., Kießling M.:
Approximate Computing Extensions for the Clash HDL Compiler
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (virtuelle Konferenz, 18. March 2021 - 19. March 2021)
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Keszöcze O., Mohammadzadeh N., Wille R.:
Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures
Design, Automation and Test in Europe (virtual conference, 1. February 2021 - 5. November 2020)
DOI: 10.23919/date51398.2021.9474188
URL: https://www.date-conference.com/
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Khosravi F., Raß A., Teich J.:
Efficient Computation of Probabilistic Dominance in Multi-objective Optimization
In: ACM Transactions on Evolutionary Learning and Optimization 1 (2021), p. 1-26
ISSN: 2688-299X
DOI: 10.1145/3469801
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Letras M., Falk J., Teich J.:
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications
24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (München, 18. March 2021 - 19. March 2021)
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Lippold D., Kergaßner A., Burkhardt C., Kergaßner M., Loos J., Nistler S., Steinmann P., Budday D., Budday S.:
Spatiotemporal modeling of first and second wave outbreak dynamics of COVID‐19 in Germany
In: Biomechanics and Modeling in Mechanobiology (2021)
ISSN: 1617-7959
DOI: 10.1007/s10237-021-01520-x
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Mohammadzadeh N., Wille R., Keszöcze O.:
Efficient One-Pass Synthesis for Digital Microfluidic Biochips
In: ACM Transactions on Design Automation of Electronic Systems (2021)
ISSN: 1084-4309
DOI: 10.1145/3446880
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Muradi M.:
Heuristische Algorithmen zur automatischen Generierung von prozesszeitoptimierten Roboterprogrammen im Bereich von Multi-Robotersystemen (Dissertation, 2021)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-159014
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Mühlenthaler M., Raß A., Schmitt M., Wanka R.:
Exact Markov chain-based runtime analysis of a discrete particle swarm optimization algorithm on sorting and OneMax
In: Natural Computing (2021)
ISSN: 1567-7818
DOI: 10.1007/s11047-021-09856-0
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Plagwitz P., Hannig F., Ströbel M., Strohmeyer C., Teich J.:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Virtual Conference, 9. May 2021 - 12. May 2021)
In: Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2021
DOI: 10.1109/FCCM51124.2021.00010
URL: https://ieeexplore.ieee.org/document/9444092
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Pourmohseni B.:
System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems (Dissertation, 2021)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-178822
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Qiao B.:
System-Level Optimization and Code Generation for Graphics Processors using a Domain-Specific Language (Dissertation, 2021)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-179475
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Qiao B., Teich J., Hannig F.:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning
2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (Portland, OR, 17. May 2021 - 21. May 2021)
In: Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) 2021
DOI: 10.1109/IPDPSW52791.2021.00067
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Sabih M., Hannig F., Teich J.:
Fault-Tolerant Low-Precision DNNs using Explainable AI
Workshop on Dependable and Secure Machine Learning (DSML) (Virtual Workshop, 21. June 2021 - 24. June 2021)
In: 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) 2021
DOI: 10.1109/DSN-W52860.2021.00036
URL: https://ieeexplore.ieee.org/document/9502445/
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Schlumberger J., Wildermann S., Teich J.:
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis
In: IEEE (ed.): 2nd IFIP NTMS Workshop on CyberSecurity on Hardware 2021 (CyberSECHARD'21), 2021, p. 1-5
DOI: 10.1109/NTMS49979.2021.9432644
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Schuster A., Heidorn C., Brand M., Keszöcze O., Teich J.:
Design Space Exploration of Time, Energy, and Error Rate Trade-oﬀs for CNNs using Accuracy-Programmable Instruction Set Processors
2nd International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM) (Virtual Event, 13. September 2021 - 17. September 2021)
In: Springer, Cham (ed.): Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021), Switzerland: 2021
DOI: 10.1007/978-3-030-93736-2_29
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Sixdenier PL.:
Towards an Autonomous, Power-Efficient Base Station for Sensor Data Collection
2nd IEEE International Conference on Autonomic Computing and Self-Organizing Systems, ACSOS 2021
In: 2nd IEEE International Conference on Autonomic Computing and Self-Organizing Systems Companion, ACSOS-C 2021 2021
DOI: 10.1109/ACSOS-C52956.2021.00083
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Smirnov F., Pourmohseni B., Fahringer T.:
Apollo: Modular and Distributed Runtime System for Serverless Function Compositions on Cloud, Edge, and IoT Resources
1st Workshop on High Performance Serverless Computing, HiPS 2021 - Co-located with HPDC 2021 (Virtual, Online, SWE, 25. June 2021)
In: HiPS 2021 - Proceedings of the 1st Workshop on High Performance Serverless Computing, co-located with HPDC 2021 2021
DOI: 10.1145/3452413.3464793
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Smirnov F., Pourmohseni B., Glaß M., Teich J.:
Efficient Symbolic Routing Encoding for In-vehicle Network Optimization
In: Smart Cities, Green Technologies and Intelligent Transport Systems, Springer, 2021, p. 173 - 199
ISBN: 978-3-030-68028-2
DOI: 10.1007/978-3-030-68028-2_9
URL: https://link.springer.com/chapter/10.1007/978-3-030-68028-2_9
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Spieck J., Wildermann S., Teich J.:
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs
3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) (North Carolina State University, Raleigh, NC, USA & Online, 31. August 2021 - 2. September 2021)
In: 3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) 2021
DOI: 10.1109/MLCAD52597.2021.9531269
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Streit FJ., Krüger P., Becher A., Schlumberger J., Wildermann S., Teich J.:
CHOICE – A Tunable PUF-Design for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Dresden, Germany, 30. August 2021 - 3. September 2021)
In: IEEE Proceedings of the 31th International Conference on Field Programmable Logic and Applications 2021
DOI: 10.1109/FPL53798.2021.00015
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Streit FJ., Krüger P., Becher A., Wildermann S., Teich J.:
Design and Evaluation of a Tunable PUF Architecture for FPGAs
In: ACM Transactions on Reconfigurable Technology and Systems 15 (2021), p. 1-27
ISSN: 1936-7406
DOI: 10.1145/3491237
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Streit FJ., Krüger P., Becher A., Wildermann S., Teich J.:
Design and Evaluation of a Tunable PUF Architecture for FPGAs
International Conference on Field-Programmable Technology (FPT) (Auckland, New Zealand, 6. December 2021 - 10. December 2021)
In: IEEE Proceedings of the 20th International Conference on Field-Programmable Technology 2021
DOI: 10.1109/ICFPT52863.2021
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Streit FJ., Wildermann S., Pschyklenk M., Teich J.:
Providing Tamper-Secure SoC Updates through Reconfigurable Hardware
International Symposium on Applied Reconfigurable Computing (ARC) (Rennes, France, 29. June 2021 - 1. July 2021)
In: Springer Proceedings of the 17th International Symposium on Applied Reconfigurable Computing 2021
DOI: 10.1007/978-3-030-79025-7_17
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Traiola M., Echavarria Gutiérrez JA., Bosio A., Teich J., O'Connor I.:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
International Conference On Computer Aided Design (Virtual conference, 1. November 2021 - 4. November 2021)
In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2021
DOI: 10.1109/iccad51958.2021.9643561
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Walter D., Teich J.:
LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays
19th ACM-IEEE International Conference on Formal Methods and Models for System Design (Beijing, China, 20. November 2021 - 22. November 2021)
In: Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2021
DOI: 10.1145/3487212.3487349
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Witterauf M.:
A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays (Dissertation, 2021)
URL: https://opus4.kobv.de/opus4-fau/files/17754/MichaelWitteraufDissertation.pdf
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Witterauf M., Walter D., Hannig F., Teich J.:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays
In: ACM Transactions on Embedded Computing Systems (2021)
ISSN: 1539-9087
DOI: 10.1145/3466897
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Özkan MA., Ok B., Qiao B., Teich J., Hannig F.:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation
In: Journal of Real-Time Image Processing 18 (2021), p. 765 - 777
ISSN: 1861-8200
DOI: 10.1007/s11554-020-01015-5
URL: http://link.springer.com/article/10.1007/s11554-020-01015-5
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Aliee H., Glaß M., Khosravi F., Teich J.:
Uncertainty-Aware Compositional System-Level Reliability Analysis
In: Henkel, Jörg, Dutt, Nikil (ed.): Dependable Embedded Systems, 2020
ISBN: 978-3-030-52017-5
DOI: 10.1007/978-3-030-52017-5_19
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Arvind TKR., Brand M., Heidorn C., Boppu S., Hannig F., Teich J.:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats
24th International Symposium on VLSI Design and Test (VDAT) (Bhubaneswar, 23. July 2020 - 25. July 2020)
In: Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT) 2020
DOI: 10.1109/VDAT50263.2020.9190305
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Bassimir B., Schmitt M., Wanka R.:
Self-adaptive potential-based stopping criteria for Particle Swarm Optimization with forced moves
In: Swarm Intelligence (2020)
ISSN: 1935-3812
DOI: 10.1007/s11721-020-00185-z
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Beena Gopalakrishnan Nair L., Becher A., Meyer-Wegener K.:
The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS
16th International Workshop on Data Management on New Hardware Held with ACM SIGMOD/PODS 2020 (Portland, Oregon USA, 15. June 2020 - 15. June 2020)
In: DaMoN '20: Proceedings of the 16th International Workshop on Data Management on New Hardware 2020
DOI: 10.1145/3399666.3399926
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Beena Gopalakrishnan Nair L., Becher A., Meyer-Wegener K., Wildermann S., Teich J.:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide
23rd International Conference on Extending Database Technology (Copenhagen, 30. March 2020 - 2. April 2020)
In: Proceedings of EDBT 2020
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Brand M., Witterauf M., Bosio A., Teich J.:
Anytime Floating-Point Addition and Multiplication – Concepts and Implementations
Conference on Application-specific Systems, Architectures and Processors (ASAP 2020) (Manchester, U.K., 6. July 2020 - 8. July 2020)
In: Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors 2020
DOI: 10.1109/ASAP49362.2020.00034
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Brand P., Sabih M., Falk J., Ah Sue J., Teich J.:
Clustering-Based Scenario-Aware LTE Grant Prediction
IEEE Wireless Communications and Networking Conference (WCNC2020) (Seoul, 25. May 2020 - 28. May 2020)
In: IEEE (ed.): Proceedings of the 2020 IEEE Wireless Communications and Networking Conference (WCNC) 2020
DOI: 10.1109/WCNC45663.2020.9120789
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Echavarria Gutiérrez JA., Wildermann S., Keszöcze O., Teich J.:
Probabilistic Error Propagation through Approximated Boolean Networks
57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. July 2020 - 23. July 2020)
In: Proceedings of the 57th Annual Design Automation Conference 2020
DOI: 10.1109/dac18072.2020.9218536
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Echavarria Gutiérrez JA., Wildermann S., Khosravi F., Teich J.:
An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy
AxC20: 5th Workshop on Approximate Computing (San Francisco, CA, 19. July 2020 - 24. July 2020)
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Fickenscher J.:
Performance Modeling and Parallelization of Environment Perception and Path Planning Algorithms for Heterogeneous Advanced Driver Assistance System Architectures (Dissertation, 2020)
BibTeX: Download
Groth S., Grünewald D., Teich J., Hannig F.:
A Runtime System for Finite Element Methods in a Partitioned Global Address Space
ACM International Conference on Computing Frontiers 2020 (Catania, Sicily, Italy, 11. May 2020 - 13. May 2020)
In: Proceedings of the 17th ACM International Conference on Computing Frontiers (CF) 2020
DOI: 10.1145/3387902.3392628
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Hannig F., Navaridas J., Koch D., Abdelhadi A. (ed.):
Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
2020
ISBN: 978-1-7281-7147-0
DOI: 10.1109/ASAP49362.2020
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Heidorn C., Hannig F., Teich J.:
Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs
International Workshop on Software and Compilers for Embedded Systems (SCOPES) (St. Goar, 25. May 2020 - 26. May 2020)
In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
DOI: 10.1145/3378678.3391878
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Herkersdorf A., Engel M., Glaß M., Henkel J., Kleeberger VB., Kühn JM., Marwedel P., Mueller-Gritschneder D., Nassif SR., Rehman S., Rosenstiel W., Schlichtmann U., Shafique M., Teich J., Wehn N., Weis C.:
RAP Model - Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience
In: Henkel, Jörg, Dutt, Nikil (ed.): Dependable Embedded Systems, 2020
ISBN: 978-3-030-52017-5
DOI: 10.1007/978-3-030-52017-5_1
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Kergaßner A., Burkhardt C., Lippold D., Kergaßner M., Pflug L., Budday D., Steinmann P., Budday S.:
Memory-based meso-scale modeling of Covid-19
In: Computational Mechanics (2020)
ISSN: 0178-7675
DOI: 10.1007/s00466-020-01883-5
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Keszöcze O., Keiner B., Richter M., Antpöhler G., Wille R.:
(Semi)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications
In: Mathias Soeken, Rolf Drechsler (ed.): Natural Language Processing for Electronic Design Automation, Springer, 2020
ISBN: 978-3-030-52271-1
DOI: 10.1007/978-3-030-52273-5
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Keszöcze O., König M., Brand M., Teich J.:
Error Analysis for Loop Programs using Anytime Instructions in Approximate Computing
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Stuttgart, 19. March 2020 - 20. March 2020)
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Keszöcze O., Schmitz K., Schloeter J., Drechsler R.:
Improving SAT Solving Using Monte Carlo Tree Search-based Clause Learning
In: Rolf Drechsler, Mathias Soeken (ed.): Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems, Springer International Publishing, 2020
ISBN: 978-3-030-20322-1
DOI: 10.1007/978-3-030-20323-8
URL: https://www.springerprofessional.de/advanced-boolean-techniques/16907760
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Keszöcze O., Wille R., Drechsler R.:
One-pass Synthesis for Digital Microfluidic Biochips: A Survey
International Symposium on Devices, Circuits and Systems (Indian Institute of Engineering Science and Technology, Shibpur, Kolkata, 4. March 2020 - 6. March 2020)
DOI: 10.1109/ISDCS49393.2020.9263007
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Lengauer C., Apel S., Bolten M., Chiba S., Rüde U., Teich J., Größlinger A., Hannig F., Köstler H., Claus L., Grebhahn A., Groth S., Kronawitter S., Kuckuk S., Rittich H., Schmitt C., Schmitt J.:
ExaStencils: Advanced multigrid solver generation
In: Hans-Joachim Bungartz, Severin Reiz, Benjamin Uekermann, Philipp Neumann, Wolfgang E. Nagel (ed.): Lecture notes in computational science and engineering, Cham: Springer, 2020, p. 405-452 (Software for Exascale Computing SPPEXA 2016 – 2019, Vol.136)
ISBN: 978-3-030-47955-8
DOI: 10.1007/978-3-030-47956-5
URL: https://library.oapen.org/bitstream/handle/20.500.12657/41289/2020_Book_SoftwareForExascaleComputing-S.pdf?sequence=1#page=411
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Lengauer C., Apel S., Bolten M., Chiba S., Rüde U., Teich J., Größlinger A., Hannig F., Köstler H., Claus L., Grebhahn A., Groth S., Kronawitter S., Kuckuk S., Rittich H., Schmitt C., Schmitt J.:
ExaStencils – Advanced Multigrid Solver Generation
In: Hans-Joachim Bungartz, Severin Reiz, Philipp Neumann, Benjamin Uekermann, Wolfgang Nagel (ed.): Software for Exascale Computing – SPPEXA 2016-2019, Springer, 2020, p. 405-452 (Lecture Notes in Computer Science and Engineering, Vol.136)
ISBN: 978-3-030-47955-8
DOI: 10.1007/978-3-030-47956-5_14
URL: https://www12.cs.fau.de/downloads/hannig/publications/ExaStencils_Advanced_Multigrid_Solver_Generation.pdf
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Letras M., Bustio L., Cumplido R., Hernández-León R., Feregrino C.:
On the design of hardware architectures for parallel frequent itemsets mining
In: Expert Systems With Applications 157 (2020)
ISSN: 0957-4174
DOI: 10.1016/j.eswa.2020.113440.
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Letras M., Falk J., Schwarzer T., Teich J.:
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements
In: ACM Transactions on Design Automation of Electronic Systems 26 (2020), p. 1–33
ISSN: 1084-4309
DOI: 10.1145/3431814
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Lukac M., Nursultan S., Krylov G., Keszöcze O.:
Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout
Euromicro Conference on Digital System Design
DOI: 10.1109/dsd51259.2020.00074
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Lukac M., Nursultan S., Krylov G., Keszöcze O.:
Refactoring of Quantum and Reversible Circuits
International Workshop on Quantum Compilation (Cambridge, 23. September 2020 - 24. September 2020)
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Mattauch S., Lohmann K., Hannig F., Lohmann D., Teich J.:
A Bibliometric Approach for Detecting the Gender Gap in Computer Science
In: Communications of the ACM 63 (2020), p. 39-45
ISSN: 0001-0782
DOI: 10.1145/3376901
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Muradi M., Wanka R.:
Processing Time Optimization for Robot Applications
6th International Conference on Control, Automation and Robotics (ICCAR) (Singapore, 20. April 2020 - 23. April 2020)
In: IEEE (ed.): Proc. 6th International Conference on Control, Automation and Robotics (ICCAR) 2020
DOI: 10.1109/ICCAR49639.2020.9108089
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Muradi M., Wanka R.:
Sample-Based Motion Planning for Multi-Robot Systems
6th International Conference on Control, Automation and Robotics (ICCAR) (Singapore, 20. April 2020 - 23. April 2020)
In: IEEE (ed.): Proc. 6th International Conference on Control, Automation and Robotics (ICCAR) 2020
DOI: 10.1109/ICCAR49639.2020.9108020
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Pourmohseni B., Glaß M., Henkel J., Khdr H., Rapp M., Richthammer V., Schwarzer T., Smirnov F., Spieck J., Teich J., Weichslgartner A., Wildermann S.:
Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective
In: Journal of Low Power Electronics and Applications 10 (2020), p. 1-37
ISSN: 2079-9268
DOI: 10.3390/jlpea10040038
URL: https://www.mdpi.com/892470
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Pourmohseni B., Smirnov F., Wildermann S., Teich J.:
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems
Workshop on Next Generation Real-Time Embedded Systems (NG-RES) (Bologna, 21. January 2020)
In: Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES) 2020
DOI: 10.4230/OASIcs.NG-RES.2020.5
URL: https://drops.dagstuhl.de/opus/volltexte/2020/11781/
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Pourmohseni B., Teich J.:
System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems
PhD Forum at the Design, Automation, and Test in Europe (DATE) Conference and Exhibition (Grenoble, France, 9. March 2020 - 13. March 2020)
URL: https://www12.cs.fau.de/downloads/pourmohseni/pub/phdForumDATE20.pdf
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Qiao B., Reiche O., Teich J., Hannig F.:
Unveiling Kernel Concurrency in Multiresolution Filters on GPUs with an Image Processing DSL
13th Workshop on General Purpose Processing Using GPU (GPGPU) (San Diego, CA, USA, 23. February 2020 - 23. February 2020)
In: Proceedings of the 13th Workshop on General Purpose Processing Using GPU (GPGPU) 2020
DOI: 10.1145/3366428.3380773
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Qiao B., Reiche O., Özkan MA., Teich J., Hannig F.:
Efficient Parallel Reduction on GPUs with Hipacc
23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 25. May 2020 - 26. May 2020)
In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
DOI: 10.1145/3378678.3391885
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Qiao B., Özkan MA., Teich J., Hannig F.:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL
57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. July 2020 - 23. July 2020)
In: Proceedings of the 57th Annual Design Automation Conference (DAC) 2020
DOI: 10.1109/DAC18072.2020.9218531
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Raß A.:
High Precision Particle Swarm Optimization Algorithm (HiPPSO)
In: Journal of Open Research Software 8 (2020), p. 4
ISSN: 2049-9647
DOI: 10.5334/jors.282
URL: https://openresearchsoftware.metajnl.com/articles/10.5334/jors.282/
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Sabih M., Hannig F., Teich J.:
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks
(2020)
Open Access: https://arxiv.org/pdf/2008.09072
URL: https://arxiv.org/abs/2008.09072
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(online publication)
Schwarzer T.:
System-level Mapping of Dataflow Applications onto MPSoCs (Dissertation, 2020)
BibTeX: Download
Simon B., Falk J., Megow N., Teich J.:
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice
Workshop on Next Generation Real-Time Embedded Systems (Bologna, 21. January 2020)
In: Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES) 2020
DOI: 10.4230/OASIcs.NG-RES.2020.2
URL: https://drops.dagstuhl.de/opus/volltexte/2020/11778/
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Smirnov F., Pourmohseni B., Teich J.:
Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems
Design, Automation and Test in Europe Conference and Exhibition (DATE) (Grenoble)
In: PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), NEW YORK: 2020
DOI: 10.23919/date48585.2020.9116383
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Smirnov F., Pourmohseni B., Teich J.:
Using Learning Classifier Systems for the DSE of Dynamically Adaptable Embedded Systems
Design, Automation and Test in Europe Conference (Grenoble, 9. March 2020 - 13. March 2020)
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Spieck J., Wildermann S., Teich J.:
Run-Time Scenario-Based MPSoC Mapping Reconfiguration Using Machine Learning Models
1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) (Canmore, Alberta, Canada, 3. September 2019 - 4. September 2019)
In: Post-workshop proceedings of 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD 2020
DOI: 10.1109/MLCAD48534.2019.9142060
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Spieck J., Wildermann S., Teich J.:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs
57th Annual Design Automation Conference (DAC) (San Francisco, 19. July 2020 - 23. July 2020)
In: Proceedings of the 57th Annual Design Automation Conference (DAC) 2020
DOI: 10.1109/DAC18072.2020.9218537
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Streit FJ., Fritz F., Becher A., Wildermann S., Werner S., Schmidt-Korth M., Pschyklenk M., Teich J.:
Secure Boot from Non-Volatile Memory for Programmable SoC-Architectures
International Symposium on Hardware Oriented Security and Trust (HOST) (San José, USA, 7. December 2020 - 11. December 2020)
In: IEEE Proceedings of the 13th International Symposium on Hardware Oriented Security and Trust 2020
DOI: 10.1109/HOST45689.2020.9300126
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Streit FJ., Wituschek S., Pschyklenk M., Becher A., Lechner M., Wildermann S., Pitz I., Merklein M., Teich J.:
Data acquisition and control at the edge: a hardware/software-reconfigurable approach
In: Production Engineering 14 (2020), p. 365-371
ISSN: 0944-6524
DOI: 10.1007/s11740-020-00964-x
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Teich J., Mahmoody P., Pourmohseni B., Roloff S., Schröder-Preikschat W., Wildermann S.:
Run-Time Enforcement of Non-functional Program Properties on MPSoCs
In: Jian-Jia Chen (ed.): A Journey of Embedded and Cyber-Physical Systems, Springer, 2020
ISBN: 978-3-030-47487-4
DOI: 10.1007/978-3-030-47487-4
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Teich J., Pourmohseni B., Keszöcze O., Spieck J., Wildermann S.:
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems
Asia and South Pacific Design Automation Conference (ASP-DAC) (China National Convention Center, Beijing, China, 13. January 2020 - 16. January 2020)
DOI: 10.1109/ASP-DAC47756.2020.9045536
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Traiola M., Echavarria Gutiérrez JA., Bosio A., Teich J., O'Connor I.:
Design Space Exploration of an Approximation-Based Fully Reliable TMR Alternative
8th Prague Embedded Systems Workshop (Horoměřice, 6. November 2020 - 7. November 2020)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Design_Space_Exploration_of_an_Approximation-Based_Fully_Reliable_TMR_Alternative.pdf
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Walter D., Witterauf M., Teich J.:
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays
18th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2020 (Jaipur, India, 2. December 2020 - 4. December 2020)
In: Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2020
DOI: 10.1109/MEMOCODE51338.2020.9315179
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Wang B., Glaß M., Falk J., Ahmed I., Teich J.:
Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs
33rd International Conference on Architecture of Computing Systems (ARCS) (Aachen, 25. May 2020 - 28. May 2020)
In: In Proc. of the 33rd International Conference on Architecture of Computing Systems (ARCS) 2020
DOI: 10.1007/978-3-030-52794-5_12
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Wendler A., Keszöcze O.:
A fast BDD Minimization Framework for Approximate Computing
Design, Automation and Test in Europe (ALPEXPO, Grenoble, France, 9. March 2020 - 13. March 2020)
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Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Leißa R., Hack S., Teich J., Hannig F.:
AnyHLS: High-Level Synthesis with Partial Evaluation
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Hamburg, 20. September 2020 - 25. September 2020)
DOI: 10.1109/tcad.2020.3012172
URL: https://arxiv.org/pdf/2002.05796.pdf
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Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Leißa R., Hack S., Teich J., Hannig F.:
AnyHLS: High-Level Synthesis with Partial Evaluation
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 (2020), p. 3202-3214
ISSN: 0278-0070
DOI: 10.1109/TCAD.2020.3012172
URL: https://arxiv.org/pdf/2002.05796.pdf
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Ah Sue J., Brand P., Falk J., Hasholzner R., Teich J.:
Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and its Application to Cellular Modems
21st Int. Conf. on Human-Computer Interaction (Orlando, Florida, USA, 26. July 2019 - 31. July 2019)
In: HCII 2019 Late Breaking Work Papers Proceedings, New York, NY, USA: 2019
DOI: 10.1007/978-3-030-30033-3_10
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Aliee H., Khosravi F., Teich J.:
Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures
Dependable Systems and Networks (DSN) (Portland, Oregon, USA, 24. June 2019 - 27. June 2019)
In: The 49th IEEE/IFIP International Conference on Dependable Systems and Networks 2019
DOI: 10.1109/dsn.2019.00022
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Bassimir B., Raß A., Schmitt M.:
Theory of particle swarm optimization: A survey of the power of the swarm’s potential
In: it - Information Technology 61 (2019), p. 169–176
ISSN: 1611-2776
DOI: 10.1515/itit-2019-0004
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Bassimir B., Wanka R.:
Robustness Approaches for the Examination Timetabling Problem under Data Uncertainty
9th Multidisciplinary International Conference on Scheduling: Theory and Applications (Ningbo)
In: Ruibin Bai, Zhi-Long Chen, Li Jiawei, Graham Kendall, Barry McCollum (ed.): Proc. 9th Multidisciplinary International Conference on Scheduling: Theory and Applications 2019
Open Access: http://www.schedulingconference.org/proceedings/2019/mista2019.pdf
URL: http://www.schedulingconference.org/proceedings/2019/mista2019.pdf
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Becher A., Herrmann A., Wildermann S., Teich J.:
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing
1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) at 18. Fachtagung für "Datenbanksysteme für Business, Technologie und Web" (Universität Rostock, 4. March 2019 - 8. March 2019)
In: Gesellschaft für Informatik, Bonn (ed.): Proceedings of the 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC), Bonn: 2019
DOI: 10.18420/btw2019-ws-04
URL: https://dl.gi.de/handle/20.500.12116/21825
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Becher A., Teich J.:
In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing
15th International Workshop on Data Management on New Hardware (DaMoN) Held with ACM SIGMOD/PODS 2019 (Amsterdam, 1. July 2019 - 1. July 2019)
DOI: 10.1145/3329785.3329936
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Brand M., Witterauf M., Hannig F., Teich J.:
Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic
ACM International Conference on Computing Frontiers 2019 (Alghero, Sardinia, 30. April 2019 - 2. May 2019)
DOI: 10.1145/3310273.3322833
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Brand M., Witterauf M., Sousa É., Tanase AP., Hannig F., Teich J.:
*-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing
In: Concurrency and Computation-Practice & Experience (2019)
ISSN: 1532-0626
DOI: 10.1002/cpe.5149
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Bustio L., Letras M., Cumplido R., Hernández-León R., Feregrino C., Bande JM.:
Using hashing and lexicographic order for Frequent Itemsets Mining on data streams
In: Journal of Parallel and Distributed Computing 125 (2019), p. 58-71
ISSN: 0743-7315
DOI: 10.1016/j.jpdc.2018.11.002.
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Echavarria Gutiérrez JA., Morales-Reyes A., Cumplido R., Salido MÁ., Feregrino C.:
IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms
In: Engineering Applications of Artificial Intelligence (2019)
ISSN: 0952-1976
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Fickenscher J., Hannig F., Teich J.:
DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs
ARCS 2019 - 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. May 2019 - 23. May 2019)
In: Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck (ed.): Proceedings of the 32nd International Conference on Architecture of Computing Systems (ARCS) 2019
DOI: 10.1007/978-3-030-18656-2
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Gabriel D., Stechele W., Wildermann S.:
Resource-aware parameter tuning for real-time applications
32nd International Conference on Architecture of Computing Systems, ARCS 2019 (Copenhagen, 20. May 2019 - 23. May 2019)
In: Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger (ed.): Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2019
DOI: 10.1007/978-3-030-18656-2_4
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Groth S., Schmitt C., Teich J., Hannig F.:
SYCL Code Generation for Multigrid Methods
22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) (Sankt Goar, Germany, 27. May 2019 - 29. May 2019)
In: 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) 2019
DOI: 10.1145/3323439.3323984
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Heidorn C., Witterauf M., Hannig F., Teich J.:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays
In: Journal of Computers 14 (2019), p. 541-556
ISSN: 1796-203X
DOI: 10.17706/jcp.14.8.541-556
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Hochradel K., Häcker T., Hohler T., Becher A., Wildermann S., Sutor A.:
Three-dimensional localization of bats: visual and acoustical
In: IEEE Sensors Journal (2019), p. 1-1
ISSN: 1530-437X
DOI: 10.1109/JSEN.2019.2907399
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Keszöcze O., Harris IG.:
Chatbot-Based Assertion Generation from Natural Language Specifications
Forum on Specification & Design Languages (FDL) (Southampton, 2. September 2019 - 4. September 2019)
DOI: 10.1109/FDL.2019.8876925
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Khosravi F.:
System-Level Reliability Analysis and Optimization in the Presence of Uncertainty (Dissertation, 2019)
BibTeX: Download
Letras M., Falk J., Schwarzer T., Teich J.:
On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures
22nd International Workshop on Software and Compilers for Embedded Systems, (SCOPES) (Sankt Goar, Germany, 27. May 2019 - 28. May 2019)
In: Proceedings of the 22st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019, Sankt Goar, Germany 2019
DOI: 10.1145/3323439.3323979
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Membarth R., Dutta H., Hannig F., Teich J.:
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards
In: Transactions on High-Performance Embedded Architectures and Compilers V, Springer, 2019, p. 1-20 (Lecture Notes in Computer Science (LNCS), Vol.11225)
ISBN: 978-3-662-58833-8
DOI: 10.1007/978-3-662-58834-5_1
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Mühlenthaler M., Raß A.:
Runtime analysis of discrete particle swarm optimization algorithms: A survey
In: it - Information Technology 61 (2019), p. 177–185
ISSN: 1611-2776
DOI: 10.1515/itit-2019-0009
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Nisar A., Ah Sue J., Teich J.:
Performance Comparison between Machine Learning based LTE Downlink Grant Predictors
21st International Conference on Artificial Intelligence (Las Vegas, 29. July 2019 - 1. August 2019)
In: Proceedings of the 21st International Conference on Artificial Intelligence 2019
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Plagwitz P., Streit FJ., Becher A., Wildermann S., Teich J.:
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs
International Conference on ReConFigurable Computing and FPGAs (ReConFig) (Cancún, Mexico, 9. December 2019 - 11. December 2019)
In: IEEE Proceedings of the 14th International Conference on ReConFigurable Computing and FPGAs 2019
DOI: 10.1109/ReConFig48160.2019.8994778
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Pourmohseni B., Smirnov F., Khdr H., Wildermann S., Teich J., Henkel J.:
Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems
IEEE Real-Time Systems Symposium (RTSS) (Hong Kong, 3. December 2019 - 6. December 2019)
In: Proceedings of the 40th IEEE Real-Time Systems Symposium (RTSS) 2019
DOI: 10.1109/RTSS46320.2019.00029
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Pourmohseni B., Smirnov F., Wildermann S., Teich J.:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems
Euromicro Conference on Real-Time Systems (ECRTS) (Stuttgart, Germany, 9. July 2019 - 12. July 2019)
In: Proceedings of the 31th Euromicro Conference on Real-Time Systems (ECRTS) 2019
DOI: 10.4230/LIPIcs.ECRTS.2019.12
URL: http://drops.dagstuhl.de/opus/volltexte/2019/10749
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Pourmohseni B., Wildermann S., Glaß M., Teich J.:
Hard Real-Time Application Mapping Reconfiguration for NoC-Based Many-Core Systems
In: Real-Time Systems (2019), p. 1-37
ISSN: 0922-6443
DOI: 10.1007/s11241-019-09326-y
URL: http://link.springer.com/article/10.1007/s11241-019-09326-y
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Qiao B., Reiche O., Hannig F., Teich J.:
From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization
2019 International Symposium on Code Generation and Optimization (CGO) (Washington, DC, USA, 16. February 2019 - 20. February 2019)
In: Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO) 2019
DOI: 10.1109/CGO.2019.8661176
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Raß A., Schreiner J., Wanka R.:
Runtime Analysis of Discrete Particle Swarm Optimization Applied to Shortest Paths Computation
19th European Conference on Evolutionary Computation in Combinatorial Optimisation (EvoCOP) (Leipzig, 24. April 2019 - 26. April 2019)
In: Springer International Publishing (ed.): Evolutionary Computation in Combinatorial Optimization, Cham: 2019
DOI: 10.1007/978-3-030-16711-0_8
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Roloff S., Hannig F., Teich J.:
ActorX10 and Run-Time Application Embedding
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 129-164 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_6
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Roloff S., Hannig F., Teich J.:
Fundamentals
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 9-40 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_2
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Roloff S., Hannig F., Teich J.:
Hybrid Network-on-Chip Simulation
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 77-99 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_4
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Roloff S., Hannig F., Teich J.:
Introduction
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 1-7 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_1
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Roloff S., Hannig F., Teich J.:
InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 41-76 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_3
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Roloff S., Hannig F., Teich J.:
Modeling and Simulation of Invasive Applications and Architectures
Singapore: Springer, 2019
(Computer Architecture and Design Methodologies)
ISBN: 978-981-13-8386-1
DOI: 10.1007/978-981-13-8387-8
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Roloff S., Hannig F., Teich J.:
Modeling and Simulation of Invasive Applications and Architectures Conclusions and Future Directions
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 165-168 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_7
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Roloff S., Hannig F., Teich J.:
Parallel MPSoC Simulation and Architecture Evaluation
In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 101-128 (Computer Architecture and Design Methodologies)
DOI: 10.1007/978-981-13-8387-8_5
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Schmitt C.:
A Domain-Specific Language and Source-to-Source Compilation Framework for Geometric Multigrid Methods (Dissertation, 2019)
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Schwarzer T., Falk J., Müller S., Letras M., Heidorn C., Wildermann S., Teich J.:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization
In: ACM Transactions on Design Automation of Electronic Systems 24 (2019), Article No.: 29
ISSN: 1084-4309
DOI: 10.1145/3310249
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Smirnov F.:
Design and Evaluation of Ethernet-based E/E-Architectures for Latency- and Safety-critical Applications (Dissertation, 2019)
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Smirnov F., Pourmohseni B., GLAß M., Teich J.:
Igor, get me the optimum! Prioritizing important design decisions during the DSE of embedded systems
In: Transactions on Embedded Computing Systems 18 (2019), Article No.: a78
ISSN: 1558-3465
DOI: 10.1145/3358204
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Smirnov F., Pourmohseni B., Glaß M., Teich J.:
IGOR, get me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems
CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis (New York, NY, 13. October 2019 - 18. October 2019)
DOI: 10.1145/3358204
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Smirnov F., Pourmohseni B., Glaß M., Teich J.:
Variety-Aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks
5th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Heraklion, Kreta, 3. May 2019 - 5. May 2019)
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Spieck J., Wildermann S., Schwarzer T., Teich J., Glaß M.:
Data-Driven Scenario-based Application Mapping for Heterogeneous Many-Core Systems
IEEE Multicore/Many-core Systems-on-Chip (Singapore, 1. October 2019 - 4. October 2019)
In: Multicore/Many-core Systems-on-Chip (MCSoC 2019) 2019
DOI: 10.1109/MCSoC.2019.00054
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Teich J., Fummi F.:
Conference Reports: Recap of DATE 2019 in Florence, Italy
In: IEEE Design & Test 36 (2019), p. 59-61
ISSN: 2168-2356
DOI: 10.1109/MDAT.2019.2915112
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Teich J., Fummi F. (ed.):
Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019
2019
ISBN: 978-3-9819263-2-3
DOI: 10.1109/MDAT.2019.2915112
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Tellabi A., Ruland C., Waedt K., Abdelbast S.:
Self diagnostics and isolation mechanisms for mixed criticality systems
In: Journal of Communications Software and Systems 15 (2019), p. 329-335
ISSN: 1845-6421
DOI: 10.24138/jcomss.v15i4.810
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Wanka R.:
Swarm Intelligence
In: it - Information Technology 61 (2019), p. 157-158
ISSN: 1611-2776
DOI: 10.1515/itit-2019-0034
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Witterauf M., Hannig F., Teich J.:
Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays
International Conference on Formal Methods and Models for System Design (MEMOCODE) (San Diego, 9. October 2019 - 11. October 2019)
In: Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE) 2019
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Xu Y., Schebesch F., Ravikumar N., Maier A.:
Detection of Unseen Low-Contrast Signals Using Classic and Novel Model Observers
Workshop on Bildverarbeitung fur die Medizin, 2019 (Lübeck, 17. March 2019 - 19. March 2019)
In: Thomas M. Deserno, Andreas Maier, Christoph Palm, Heinz Handels, Klaus H. Maier-Hein, Thomas Tolxdorff (ed.): Informatik aktuell 2019
DOI: 10.1007/978-3-658-25326-4_47
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Özkan MA., Reiche O., Qiao B., Membarth R., Teich J., Hannig F.:
Synthesizing High-Performance Image Processing Applications with Hipacc
Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Florence, 25. March 2019 - 29. March 2019)
URL: https://www12.cs.fau.de/downloads/oezkan/publications/date-ubooth19.pdf
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(online publication)

Afzal A., Schmitt C., Alhaddad S., Grynko Y., Teich J., Förstner J., Hannig F.:
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study
The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Politecnico di Milano, Milan, 10. July 2018 - 12. July 2018)
In: Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
DOI: 10.1109/ASAP.2018.8445127
URL: https://www12.cs.fau.de/downloads/schmittch/publications/ASAGTFH18asap.pdf
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Ah Sue J., Brand P., Brendel J., Hasholzner R., Falk J., Teich J.:
A Predictive Dynamic Power Management for LTE-Advanced Mobile Devices
IEEE Wireless Communications and Networking Conference (Barcelona, Catalonia, Spain, 15. April 2018 - 18. April 2018)
In: IEEE (ed.): 2018 IEEE Wireless Communications and Networking Conference (WCNC'18) 2018
DOI: 10.1109/WCNC.2018.8377189
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Aydin F., Ugurdag HF., Leyent VE., Guzel AE., Annafianto NFR., Özkan MA., Akgun T., Erbas C.:
Rapid Design of Real-Time Image Fusion on FPGA Using HLS and Other Techniques
15th IEEE/ACS International Conference on Computer Systems and Applications (AICCSA) (Aqaba, 28. October 2018 - 1. November 2018)
In: 2018 IEEE/ACS 15TH INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS (AICCSA), NEW YORK: 2018
DOI: 10.1109/aiccsa.2018.8612836
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Bassimir B., Wanka R.:
Probabilistic Curriculum-based Examination Timetabling
12th International Conference on the Practice and Theory of Automated Timetabling (PATAT) (Vienna)
In: Edmund K. Burke, Luca Di Gaspero, Barry McCollum, Nysret Musliu, Ender Özcan (ed.): Proc 12th International Conference on the Practice and Theory of Automated Timetabling (PATAT) 2018
Open Access: http://patatconference.org/patat2018/proceedings/
URL: http://patatconference.org/patat2018/files/proceedings/paper41.pdf
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Becher A., Beena Gopalakrishnan Nair L., Broneske D., Drewes T., Gurumurthy B., Meyer-Wegener K., Pionteck T., Saake G., Teich J., Wildermann S.:
Integration of FPGAs in Database Management Systems: Challenges and Opportunities
In: Datenbank-Spektrum (2018)
ISSN: 1618-2162
DOI: 10.1007/s13222-018-0294-9
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Becher A., Wildermann S., Teich J.:
Optimistic Regular Expression Matching on FPGAs for Near-Data Processing
Data Management on New Hardware (DaMoN) (Houston, Texas, 11. June 2018 - 11. June 2018)
DOI: 10.1145/3211922.3211926
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Brand P., Falk J., Ah Sue J., Brendel J., Hasholzner R., Teich J.:
Reinforcement Learning for Power-Efficient Grant Prediction in LTE
(2018), p. 18-26
DOI: 10.1145/3207719.3207722
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Echavarria Gutiérrez JA., Schütz K., Becher A., Wildermann S., Teich J.:
Can Approximate Computing Reduce Power Consumption on FPGAs?
25th IEEE International Conference on Electronics Circuits and Systems (Bordeaux, 9. December 2018 - 12. December 2018)
In: Proceedings of IEEE International Conference on Electronics Circuits and Systems 2018
DOI: 10.1109/icecs.2018.8618062
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Echavarria Gutiérrez JA., Schütz K., Becher A., Wildermann S., Teich J.:
Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
AxC18: 3rd Workshop on Approximate Computing (Swissôtel Bremen, 31. May 2018 - 1. June 2018)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Evaluation_of_Approximate_Computing_Techniques_for_Power_Reduction_on_FPGAs.pdf
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Echavarria Gutiérrez JA., Wildermann S., Teich J.:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
International Conference on Field Programmable Technology (FPT 2018) (Naha, Okinawa, 10. December 2018 - 14. December 2018)
In: Proceedings of 2018 International Conference on Field Programmable Technology 2018
DOI: 10.1109/fpt.2018.00065
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Echavarria Gutiérrez JA., Wildermann S., Teich J.:
Design Space Exploration of Multi-output Logic Function Approximations
International Conference On Computer Aided Design (ICCAD 2018) (San Diego, CA, 5. November 2018 - 8. November 2018)
In: Proceedings of the International Conference On Computer Aided Design 2018
DOI: 10.1145/3240765.3240795
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Falk J., Neubauer K., Haubelt C., Zebelein C., Teich J.:
Integrated Modeling Using Finite State Machines and Dataflow Graphs
In: Bhattacharyya S., Deprettere E., Leupers R., Takala J. (ed.): Handbook of Signal Processing Systems, Springer, 2018, p. 825-864
ISBN: 978-3-319-91734-4
DOI: 10.1007/978-3-319-91734-4_23
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Fey D., Hannig F.:
Special Issue on Heterogeneous Real-Time Image Processing
In: Journal of Real-Time Image Processing 14 (2018), p. 513-515
ISSN: 1861-8200
DOI: 10.1007/s11554-018-0763-2
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Fickenscher J., Hannig F., Bouzouraa ME., Teich J.:
Embedded GPUs in Future Automated Cars
Design, Automation and Test in Europe (DATE) (Dresden, 19. March 2018 - 23. March 2018)
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(Working Paper)
Fickenscher J., Hannig F., Teich J., Bouzouraa ME.:
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs
4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Funchal, Madeira, Portugal, 16. March 2018 - 18. March 2018)
DOI: 10.5220/0006677302980306
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Fickenscher J., Schlumberger J., Hannig F., Bouzouraa ME., Teich J.:
Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs
Design, Automation and Test in Europe (DATE) (Dresden, Germany, 19. March 2018 - 23. March 2018)
DOI: 10.23919/DATE.2018.8342050
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Fickenscher J., Schmidt S., Hannig F., Bouzouraa ME., Teich J.:
Path Planning for Highly Automated Driving on Embedded GPUs
4 (2018)
ISSN: 2079-9268
DOI: 10.3390/jlpea8040035
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Henkel J., Teich J., Wildermann S., Amrouch H.:
Dynamic Resource Management for Heterogeneous Many-Cores
International Conference On Computer Aided Design (ICCAD 2018) (San Diego, CA, 5. November 0018 - 8. November 0018)
In: Proceedings of International Conference On Computer Aided Design 2018 2018
DOI: 10.1145/3240765.3243471
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Hochradel K., Hohler T., Becher A., Wildermann S., Sutor A.:
Development of a multisensor array for localizing bats in space
In: Journal of Physics: Conference Series 1065 (2018), p. 072014
ISSN: 1742-6588
DOI: 10.1088/1742-6596/1065/7/072014
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Kenter T., Mahale G., Alhaddad S., Grynko Y., Schmitt C., Afzal A., Hannig F., Förstner J., Plessl C.:
OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Boulder, CO, USA, 29. April 2018 - 1. May 2018)
In: Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2018
DOI: 10.1109/FCCM.2018.00037
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Keszöcze O., Soeken M., Drechsler R.:
Computational Complexity of Error Metrics in Approximate Computing
In: Bernd Steinbach (ed.): Further Improvements in the Boolean Domain, 2018, p. Cambridge Scholars Publishing
ISBN: 978-1-5275-0371-7
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Keszöcze O., Wille R., Drechsler R.:
Exact Design of Digital Microfluidic Biochips
Springer, 2018
ISBN: 978-3-319-90936-3
URL: https://www.springer.com/us/book/9783319909356
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Khosravi F., Borst M., Teich J.:
Probabilistic Dominance in Robust Multi-Objective Optimization
IEEE Congress on Evolutionary Computation (CEC) (Barra da Tijuca, Rio de Janeiro, 8. July 2018 - 13. July 2018)
In: IEEE Congress on Evolutionary Computation (CEC) 2018
DOI: 10.1109/CEC.2018.8477676
URL: https://ieeexplore.ieee.org/abstract/document/8477676
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Khosravi F., Müller M., Glaß M., Teich J.:
Simulation-based Uncertainty Correlation Modeling in Reliability Analysis
In: Proceedings of the Institution of Mechanical Engineers, Part O: Journal of Risk and Reliability 232 (2018), p. 725-737
ISSN: 1748-006X
DOI: 10.1177/1748006X18758720
URL: https://journals.sagepub.com/doi/abs/10.1177/1748006X18758720
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Mattauch S., Lohmann K., Hannig F., Lohmann D., Teich J.:
The Gender Gap in Computer Science --- A Bibliometric Analysis
(2018)
ISSN: 2191-5008
DOI: 10.25593/issn.2191-5008/CS-2018-02
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(Techreport)
Mercader A., Ah Sue J., Hasholzner R., Brendel J.:
Improvements in LTE-Advanced Time Series Prediction with Dimensionality Reduction Algorithms
IEEE 5G World Forum (Santa Clara, CA, 9. July 2018 - 11. July 2018)
In: IEEE (ed.): Proc. of the IEEE 5G World Forum 2018
DOI: 10.1109/5gwf.2018.8516973
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Mitra T., Teich J., Thiele L.:
Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design
In: IEEE Design and Test of Computers 35 (2018), p. 5-7
ISSN: 0740-7475
DOI: 10.1109/MDAT.2018.2796037
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Mitra T., Teich J., Thiele L.:
Guest Editors’ Introduction: Special Issue on Time-Critical Systems Design Part II
In: IEEE Design and Test of Computers 35 (2018), p. 5 - 6
ISSN: 0740-7475
DOI: 10.1109/MDAT.2018.2841769
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Mitra T., Teich J., Thiele L.:
Time-Critical Systems Design: A Survey
In: IEEE Design and Test of Computers 35 (2018), p. 8-26
ISSN: 0740-7475
DOI: 10.1109/MDAT.2018.2794204
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Posewsky T., Ziener D.:
A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks
International Conference on Architecture of Computing Systems (Braunschweig, 9. April 2018 - 12. April 2018)
In: Proceedings of the International Conference on Architecture of Computing Systems 2018
DOI: 10.1007/978-3-319-77610-1_23
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Qiao B., Reiche O., Hannig F., Teich J.:
Automatic Kernel Fusion for Image Processing DSLs
21st International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 28. May 2018 - 30. May 2018)
In: Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2018
DOI: 10.1145/3207719.3207723
BibTeX: Download
Reiche O.:
A Domain-Specific Language Approach for Designing and Programming Heterogeneous Image Systems (Dissertation, 2018)
BibTeX: Download
Reiche O., Özkan MA., Hannig F., Teich J., Schmid M.:
Loop Parallelization Techniques for FPGA Accelerator Synthesis
In: Journal of Signal Processing Systems 90 (2018), p. 3-27
ISSN: 1939-8115
DOI: 10.1007/s11265-017-1229-7
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Richthammer V., Schwarzer T., Wildermann S., Teich J., Glaß M.:
Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems
55th ACM/EDAC/IEEE Design Automation Conference (DAC 2018) (San Francisco, CA, 24. June 2018 - 28. June 2018)
DOI: 10.1109/DAC.2018.8465811
BibTeX: Download
Roloff S.:
Modeling and Simulation of Invasive Applications and Architectures (Dissertation, 2018)
DOI: 10.1007/978-981-13-8387-8
BibTeX: Download
Schmitt C., Hannig F., Teich J.:
A Target Platform Description Language for Parallel Code Generation
31st GI/ITG International Conference on Architecture of Computing Systems (ARCS) (Braunschweig, 9. April 2018 - 12. April 2018)
In: Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS), Berlin: 2018
URL: https://www12.cs.fau.de/downloads/schmittch/publications/SHT18arcs.pdf
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Schmitt C., Kronawitter S., Hannig F., Teich J., Lengauer C.:
Automating the Development of High-Performance Multigrid Solvers
In: Proceedings of the IEEE 106 (2018), p. 1969-1984
ISSN: 0018-9219
DOI: 10.1109/JPROC.2018.2854229
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Schmitt C., Schmid M., Kuckuk S., Köstler H., Teich J., Hannig F.:
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution
In: Parallel Processing Letters 28 (2018), Article No.: 1850016
ISSN: 0129-6264
DOI: 10.1142/S0129626418500160
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Schwarzer T., Roloff S., Richthammer V., Khaldi R., Wildermann S., Glaß M., Teich J.:
On the Complexity of Mapping Feasibility in Many-Core Architectures
Multicore/Many-core Systems-on-Chip (MCSoC-2018) (Hanoi, 12. September 2018 - 14. September 2018)
In: Proceedings of Multicore/Many-core Systems-on-Chip (MCSoC-2018) 2018
DOI: 10.1109/MCSoC2018.2018.00038
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Schwarzer T., Weichslgartner A., Glaß M., Wildermann S., Brand P., Teich J.:
Symmetry-eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 (2018), p. 297-310
ISSN: 0278-0070
DOI: 10.1109/TCAD.2017.2695894
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Smirnov F., Reimann F., Teich J., Glaß M.:
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks
In: ACM Transactions on Design Automation of Electronic Systems (2018)
ISSN: 1084-4309
DOI: 10.1145/3278120
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Smirnov F., Reimann F., Teich J., Han Z., Glaß M.:
Automatic Optimization of Redundant Message Routings in Automotive Networks
21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018) (Sankt Goar, 28. May 2018 - 30. May 2018)
In: ACM (ed.): Proceedings of 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018) 2018
DOI: 10.1145/3207719.3207725
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Sousa É.:
Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation, 2018)
BibTeX: Download
Sousa É., Witterauf M., Brand M., Tanase AP., Hannig F., Teich J.:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Milan, Italy, 10. July 2018 - 12. July 2018)
DOI: 10.1109/ASAP.2018.8445109
URL: https://ieeexplore.ieee.org/abstract/document/8445109/
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Streit FJ., Letras M., Wildermann S., Hackenberg B., Falk J., Becher A., Teich J.:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancún, Mexico, 3. December 2018 - 5. December 2018)
In: IEEE Proceedings of the 13th International Conference on ReConFigurable Computing and FPGAs 2018
DOI: 10.1109/RECONFIG.2018.8641736
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Tanase AP., Hannig F., Teich J.:
Symbolic Parallelization of Nested Loop Programs
Springer, 2018
ISBN: 978-3-319-73908-3
DOI: 10.1007/978-3-319-73909-0
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Weichslgartner A., Wildermann S., Gangadharan D., Glaß M., Teich J.:
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs
In: ACM Transactions on Embedded Computing Systems (2018)
ISSN: 1539-9087
DOI: 10.1145/3274665
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Weichslgartner A., Wildermann S., Glaß M., Teich J.:
Invasive Computing for Mapping Parallel Programs to Many-Core Architectures
Springer, 2018
ISBN: 978-981-10-7355-7
DOI: 10.1007/978-981-10-7356-4
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Witterauf M., Teich J.:
Run-time Requirement Enforcement for Loop Programs on Processor Arrays
16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (Peking, 15. October 2018 - 17. October 2018)
In: ACM, IEEE (ed.): Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2018
DOI: 10.1109/MEMCOD.2018.8556911
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Ziener D., Pirkl J., Teich J.:
Configuration Tempering of BRAM-based AES Implementations on FPGAs
2018 International Conference on Reconfigurable Computing and FPGAs (Cancun, 3. December 0018 - 5. December 0018)
In: Proceedings of 2018 International Conference on Reconfigurable Computing and FPGAs 2018
DOI: 10.1109/reconfig.2018.8641692
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Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Teich J., Hannig F.:
A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement
International Workshop on FPGAs for Software Programmers (Dublin, 31. August 2018)
In: Proceedings of the Fifth International Workshop on FPGAs for Software Programmers 2018
URL: https://www12.cs.fau.de/downloads/oezkan/publications/fsp18.pdf
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Aliee H.:
Reliability Analysis and Optimization of Embedded Systems using Stochastic Logic and Importance Measures (Dissertation, 2017)
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Aliee H., Banaiyianmofrad A., Glaß M., Teich J., Dutt N.:
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'17) (Bremen, 8. February 2017 - 9. February 2017)
In: Proc. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'17) 2017
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Aliee H., Borgonovo E., Glaß M., Teich J.:
On the Boolean Extension of the Birnbaum Importance to Non-Coherent Systems
In: Reliability Engineering & System Safety 160 (2017), p. 191-200
ISSN: 0951-8320
DOI: 10.1016/j.ress.2016.12.013
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Brand M., Hannig F., Tanase AP., Teich J.:
Efficiency in ILP Processing by Using Orthogonality
The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017) (Seattle, 10. July 2017 - 12. July 2017)
In: IEEE (ed.): 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
DOI: 10.1109/ASAP.2017.7995282
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Brand M., Hannig F., Tanase AP., Teich J.:
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17) (Korea University, Seoul, Korea, 18. September 2017 - 20. September 2017)
In: 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip 2017
DOI: 10.1109/MCSoC.2017.17
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Brand P., Ah Sue J., Brendel J., Falk J., Hasholzner R., Teich J., Wildermann S.:
Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems
20th International Workshop on Software and Compilers for Embedded Systems (SCOPES’17) (Sankt Goar, Deutschland, 12. June 2017 - 13. June 2017)
In: ACM (ed.): 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES’17) 2017
DOI: 10.1145/3078659.3078670
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Bustio L., Cumplido R., Hernández-León R., Bande JM., Letras M., Feregrino C.:
Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware
8th Latin American Symposium on Circuits and Systems (LASCAS)
DOI: 10.1109/LASCAS.2017.7948076
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Echavarria Gutiérrez JA., Wildermann S., Potwigin E., Teich J.:
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders
In: IEEE Embedded Systems Letters (2017), Article No.: 99
ISSN: 1943-0663
DOI: 10.1109/LES.2017.2760922
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Falk J., Haubelt C., Teich J., Zebelein C.:
SysteMoC: A Data-Flow Programming Language for Codesign
In: Ha S, Teich J (ed.): Handbook of Hardware/Software Codesign, Dordrecht, The Netherlands: Springer, 2017, p. 59 - 97
ISBN: 978-94-017-7266-2
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Fickenscher J., Bouzouraa ME., Hannig F., Teich J.:
Environment Mapping Using Massively Parallel Architectures
Vehicle Intelligence (München, 5. December 2017 - 7. December 2017)
BibTeX: Download
Fickenscher J., Reinhart S., Bouzouraa ME., Hannig F., Teich J.:
Convoy Tracking for ADAS on Embedded GPUs
Intelligent Vehicles Symposium (IV 2017) (Redondo Beach, CA, USA, 11. June 2017 - 14. June 2017)
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Glaß M., Teich J., Lukasiewycz M., Reimann F.:
Hybrid Optimization Techniques for System-Level Design Space Exploration
In: Ha S, Teich J (ed.): Handbook of Hardware/Software Codesign, Dordrecht, The Netherlands: Springer, 2017, p. 217-246
ISBN: 978-94-017-7266-2
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Ha S., Teich J.:
The Handbook of Hardware/Software Codesign
Springer, 2017
DOI: 10.1007/978-94-017-7267-9_4
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Ha S., Teich J., Haubelt C., Glaß M., Mitra T., Dömer R., Eles P., Shrivastava A., Gerstlauer A., Bhattacharyya SS.:
Introduction to Hardware/Software Codesign
In: Ha S, Teich J (ed.): Handbook of Hardware/Software Codesign, Dordrecht, The Netherlands: Springer, 2017, p. 3-26
ISBN: 978-94-017-7266-2
DOI: 10.1007/978-94-017-7267-9
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Hannig F.:
Domain-specific and Resource-aware Computing (Habilitation, 2017)
DOI: 10.13140/RG.2.2.23418.13761
URL: https://www.cs12.tf.fau.de/files/2016/08/Frank_Hannig_Habilitation2017.pdf
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Khdr H., Pagani S., Rodrigues Sousa E., Lari V., Pathania A., Hannig F., Shafique M., Teich J., Henkel J.:
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
In: IEEE Transactions on Computers 66 (2017), p. 488--501
ISSN: 0018-9340
DOI: 10.1109/TC.2016.2595560
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Khosravi F., Aliee H., Teich J.:
System-Level Reliability Analysis Considering Imperfect Fault Coverage
15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (Seoul, Republic of Korea, 15. October 2017 - 20. October 2017)
In: 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2017
DOI: 10.1145/3139315.3141787
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Khosravi F., Glaß M., Teich J.:
Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures
In: IEEE Transactions on Reliability 66 (2017), p. 319-338
ISSN: 0018-9529
DOI: 10.1109/TR.2016.2638320
URL: http://ieeexplore.ieee.org/document/7805166/
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Kuckuk S., Leitenmaier L., Schmitt C., Schönwetter D., Köstler H., Fey D.:
Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers
CS 2017-01 (2017), p. 1-8
ISSN: 2191-5008
Open Access: http://nbn-resolving.de/urn:nbn:de:bvb:29-opus4-83179
URL: http://nbn-resolving.de/urn:nbn:de:bvb:29-opus4-83179
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(Techreport)
Köstler H., Schmitt C., Kuckuk S., Kronawitter S., Hannig F., Teich J., Rüde U., Lengauer C.:
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms
In: International Journal of Computational Science and Engineering 14 (2017), p. 150-163
ISSN: 1742-7185
DOI: 10.1504/IJCSE.2017.10003829
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Letras M., Falk J., Wildermann S., Teich J.:
Automatic Conversion of Simulink Models to SysteMoC Actor Networks
20th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 12. June 2017 - 13. June 2017)
DOI: 10.1145/3078659.3078668
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Li Z., Park H., Malik A., Wang KI., Salcic Z., Kuzmin B., Glaß M., Teich J.:
Using Design Space Exploration for Finding Schedules with Guaranteed Reaction Times of Synchronous Programs on Multi-core Architecture
In: Journal of Systems Architecture 74 (2017), p. 30-45
ISSN: 1383-7621
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Mühlenthaler M., Raß A., Schmitt M., Siegling A., Wanka R.:
Runtime Analysis of a Discrete Particle Swarm Optimization Algorithm on Sorting and OneMax
Conference on Foundations of Genetic Algorithms (FOGA) (Copenhagen, Denmark, 12. January 2017 - 15. January 2017)
In: ACM New York, NY, USA (ed.): Proceedings of the 14th ACM/SIGEVO Conference on Foundations of Genetic Algorithms 2017
DOI: 10.1145/3040718.3040721
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Pirkl J., Becher A., Echavarria Gutiérrez JA., Teich J., Wildermann S.:
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics
20th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 12. June 2017 - 13. June 2017)
In: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems 2017
DOI: 10.1145/3078659.3078669
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Pourmohseni B., Glaß M., Teich J.:
Automatic Operating Point Distillation for Hybrid Mapping Methodologies
Design, Automation & Test in Europe Conference & Exhibition (DATE) (Lausanne, 27. March 2017 - 31. March 2017)
In: Proceedings of the 20th Design, Automation & Test in Europe Conference & Exhibition (DATE) 2017
DOI: 10.23919/DATE.2017.7927160
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Pourmohseni B., Wildermann S., Glaß M., Teich J.:
Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems
International Conference on Real-Time Networks and Systems (RTNS) (Grenoble, 4. October 2017 - 6. October 2017)
In: Proceedings of the 25th International Conference on Real-Time Networks and Systems (RTNS) 2017
DOI: 10.1145/3139258.3139278
URL: https://dl.acm.org/authorize?N42087
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Reiche O., Kobylko C., Hannig F., Teich J.:
Auto-vectorization for Image Processing DSLs
18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (Barcelona, 21. June 2017 - 22. June 2017)
In: Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) 2017
DOI: 10.1145/3078633.3081039
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Reiche O., Özkan MA., Membarth R., Teich J., Hannig F.:
Generating FPGA-based Image Processing Accelerators with Hipacc
International Conference on Computer Aided Design (ICCAD) (Irvine, 13. November 2017 - 16. November 2017)
In: Proceedings of the International Conference on Computer Aided Design (ICCAD) 2017
DOI: 10.1109/ICCAD.2017.8203894
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Roloff S., Hannig F., Teich J.:
High Performance Network-on-Chip Simulation by Interval-based Timing Predictions
15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (Seoul, Republic of Korea, 15. October 2017 - 20. October 2017)
In: ACM (ed.): Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2017
DOI: 10.1145/3139315.3139320
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Rosales R.:
Holistic Actor-Oriented Modeling of Embedded Systems for ESL Power Consumption Evaluation (Dissertation, 2017)
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Schmidt B., Ziener D., Teich J., Zöllner C.:
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
In: Integration-The Vlsi Journal (2017)
ISSN: 0167-9260
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Smirnov F., Glaß M., Reimann F., Teich J.:
Formal Timing Analysis of Non-Scheduled Traffic in Automotive Scheduled TSN Networks
Design, Automation and Test in Europe (DATE) (Lausanne, 27. March 2017 - 30. March 2017)
In: Proceedings of Design, Automation and Test in Europe (DATE) 2017 2017
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Smirnov F., Glaß M., Reimann F., Teich J.:
Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks
54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017) (Austin, 18. June 2017 - 22. June 2017)
In: Proceedings of 54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017) 2017
DOI: 10.1145/3061639.3062298
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Sousa É., Chakraborty A., Tanase AP., Hannig F., Teich J.:
TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays
Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 4. December 2017 - 6. December 2017)
DOI: 10.1109/RECONFIG.2017.8279818
URL: http://ieeexplore.ieee.org/document/8279818/
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Sousa É., Tanase AP., Hannig F., Teich J.:
A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays
International Conference on ReConFigurable Computing and FPGA's (ReConFig) (Cancun, Mexico, 4. December 2017 - 6. December 2017)
DOI: 10.1109/RECONFIG.2017.8279768
URL: http://ieeexplore.ieee.org/document/8279768/
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Streit FJ., Letras M., Schid M., Falk J., Wildermann S., Teich J.:
High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems
International Conference on Distributed Smart Cameras (ICDSC) (Stanford, USA, 5. September 2017 - 7. September 2017)
In: ACM Proceedings of the 11th International Conference on Distributed Smart Cameras 2017
DOI: 10.1145/3131885.3131932
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Tanase AP.:
Symbolic Parallelization of Nested Loop Programs (Dissertation, 2017)
BibTeX: Download
Tanase AP., Witterauf M., Teich J., Hannig F.:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
In: ACM Transactions on Embedded Computing Systems 17 (2017), p. 31:1-31:27
ISSN: 1539-9087
DOI: 10.1145/3092952
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Teich J.:
Run-Time Monitoring and Enforcement of Non-functional Program Properties of Invasive Programs: Terms and Definitions
(2017)
URL: https://www12.informatik.uni-erlangen.de/publications/pub2017/reportTeich17.pdf
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(Techreport)
Unat D., Dubey A., Hoefler T., Shalf J., Abraham M., Bianco M., Chamberlain BL., Cledat R., Edwards HC., Finkel H., Fürlinger K., Hannig F., Jeannot E., Kamil A., Keasler J., Kelly PHJ., Leung VJ., Ltaief H., Maruyama N., Newburn C., Pericàs M.:
Trends in Data Locality Abstractions for HPC Systems
In: IEEE Transactions on Parallel and Distributed Systems (2017)
ISSN: 1045-9219
DOI: 10.1109/TPDS.2017.2703149
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Vogel-Heuser B., Wildermann S., Teich J.:
Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems
In: Production Engineering 11 (2017), p. 687-694
ISSN: 0944-6524
DOI: 10.1007/s11740-017-0765-0
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Vogel-Heuser B., Wildermann S., Teich J.:
Towards the Co-Evolution of Industrial Products and its Production Systems by Combining Models from Development and Hardware/Software Deployment in Cyber-Physical Systems
In: Production Engineering 11 (2017), p. 687-694
ISSN: 0944-6524
DOI: 10.1007/s11740-017-0765-0
URL: https://link.springer.com/article/10.1007/s11740-017-0765-0
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Weichslgartner A.:
Application Mapping Methodologies for Invasive NoC-Based Architectures (Dissertation, 2017)
BibTeX: Download
Witterauf M., Hannig F., Teich J.:
Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates
Symposium on Rapid System Prototyping (Seoul, South Korea, 19. October 2017 - 20. October 2017)
In: Proceedings of the Symposium on Rapid System Prototyping 2017
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Zaib A., Heisswolf J., Weichslgartner A., Wild T., Teich J., Becker J., Herkersdorf A.:
Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures
In: Journal of Systems Architecture 77 (2017), p. 72-82
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2017.03.004
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Ziener D.:
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems (Habilitation, 2017)
URL: https://opus4.kobv.de/opus4-fau/files/9271/habilon.pdf
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Özkan MA., Reiche O., Hannig F., Teich J.:
A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
Fourth International Workshop on FPGAs for Software Programmers (FSP) (Ghent, 7. September 2017)
In: Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP) 2017
URL: https://ieeexplore.ieee.org/document/8084549
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Özkan MA., Reiche O., Hannig F., Teich J.:
Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Seattle, 10. July 2017 - 12. July 2017)
In: 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
DOI: 10.1109/ASAP.2017.7995273
URL: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf
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Ah Sue J., Hasholzner R., Brendel J., Kleinsteuber M., Teich J.:
A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction
10th IEEE International Conference on Self-Adaptive and Self-Organizing Systems (SASO 2016) (Augsburg, 12. September 2016 - 16. September 2016)
In: 1st International Workshops on Foundations and Applications of Self-Adaptive and Self-Organizing Systems (SASO 2016)Self-Organizing Systems (SASO 2016) 2016
DOI: 10.1109/FAS-W.2016.64
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Aliee H., Vitzethum S., Glaß M., Teich J., Borgonovo E.:
Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems
29th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (Connecticut, 19. September 2016 - 20. September 2016)
In: Proceedings of 29th IEEE Symposium on Defect and Fault Tolerance in VLSI and 2016
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Becher A., Echavarria Gutiérrez JA., Ziener D., Wildermann S., Teich J.:
A LUT-Based Approximate Adder
24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016). (Washington DC, 1. May 2016 - 3. May 2016)
In: Proceedings of the 24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines 2016
DOI: 10.1109/FCCM.2016.16
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Becher A., Pirkl J., Herrmann A., Teich J., Wildermann S.:
Hybrid Energy-Aware Reconfiguration Management on Xilinx Zynq SoCs
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancún)
In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) 2016
DOI: 10.1109/ReConFig.2016.7857177
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Becher A., Wildermann S., Mühlenthaler M., Teich J.:
ReOrder: Runtime Datapath Generation for High-Throughput Multi-Stream Processing
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancún)
In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs 2016
DOI: 10.1109/ReConFig.2016.7857185
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Bhadouria VS., Tanase AP., Schmid M., Hannig F., Teich J., Ghoshal D.:
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
In: Journal of Signal Processing Systems 89 (2016), p. 225-242
ISSN: 1939-8018
DOI: 10.1007/s11265-016-1187-5
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Borgonovo E., Aliee H., Glaß M., Teich J.:
A New Time-Independent Reliability Importance Measure
In: European Journal of Operational Research (2016)
ISSN: 0377-2217
DOI: 10.1016/j.ejor.2016.03.054
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Drescher G., Erhardt C., Freiling F., Götzfried J., Lohmann D., Maene P., Müller T., Verbauwhede I., Weichslgartner A., Wildermann S.:
Providing security on demand using invasive computing
In: it - Information Technology 58 (2016), p. 281-295
ISSN: 1611-2776
DOI: 10.1515/itit-2016-0032
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Echavarria Gutiérrez JA., Wildermann S., Becher A., Teich J., Ziener D.:
FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
International Conference on Field Programmable Technology (FPT 2016) (Xi'an, 7. December 2016 - 9. December 2016)
In: Proceedings of 2016 International Conference on Field Programmable Technology 2016
DOI: 10.1109/FPT.2016.7929536
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Fanucci L., Teich J.:
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016
In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, 2016
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Fanucci L., Teich J.:
Recap of the 2016 DATE Conference & Exhibition
In: IEEE Design and Test of Computers 33 (2016), p. 114-117
ISSN: 0740-7475
DOI: 10.1109/MDAT.2016.2570223
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Fickenscher J., Reiche O., Schlumberger J., Hannig F., Teich J.:
Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs
18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (Santa Cruz, CA, 7. October 2016 - 8. October 2016)
In: Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) 2016
DOI: 10.1109/HLDVT.2016.7748257
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Hannig F.:
A Quick Tour of High-Level Synthesis Solutions for FPGAs
In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016
DOI: 10.1007/978-3-319-26408-0_3
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Hannig F., Cardoso J., Fey D., Schröder-Preikschat W., Teich J.:
Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings
Springer Verlag, 2016
ISBN: 9783319306940
DOI: 10.1007/978-3-319-30695-7
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Hannig F., Cardoso JMP., Pionteck T., Fey D., Schröder-Preikschat W., Teich J. (ed.):
Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS)
Berlin; Heidelberg: 2016
(Lecture Notes in Computer Science (LNCS), Vol. 9637)
ISBN: 978-3-319-30694-0
DOI: 10.1007/978-3-319-30695-7
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Haubelt C., Neubauer K., Glaß M.:
Supporting Composition in Symbolic System Synthesis
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS) (Samos, 18. July 2016 - 21. July 2016)
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Heißwolf J., Friederich S., Masing L., Weichslgartner A., Zaib A., Stein C., Duden M., Teich J., Herkersdorf A., Becker J.:
A Novel NoC-Architecture for Fault Tolerance and Power Saving
Third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS (Nuremberg, 4. April 2016 - 5. April 2016)
In: In Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS 2016
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Henkel J., Chen Q., Schmitt-Landsiedel D., Glocker E., Sousa É., Schlichtmann U., Herkersdorf A., Hannig F., Wenzel V., Wagner P., Sagi M., Wild T., Khdr H., Pagani S., Pathania A., Bauer L.:
Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach
In: it - Information Technology 58 (2016), p. 297-307
ISSN: 1611-2776
DOI: 10.1515/itit-2016-0028
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Herglotz C., Rosales R., Glaß M., Teich J., Kaup A.:
Multi-Objective Design Space Exploration for the Optimization of the HEVC Mode Decision Process
Picture Coding Symposium(PCS) (Nürnberg, 4. December 2016 - 7. December 2016)
In: Picture Coding Symposium (PCS) 2016
DOI: 10.1109/PCS.2016.7906327
URL: http://arxiv.org/abs/2203.01782
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Häublein K., Reichenbach M., Reiche O., Özkan MA., Fey D., Hannig F., Teich J.:
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, 18. June 2016 - 21. June 2016)
In: Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2016
DOI: 10.1109/SAMOS.2016.7818350
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Keszöcze O., Wille R.:
Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision
In: Frank Oppenheimer, Julio Luis Medina Pasaje (ed.): Languages, Design Methods, and Tools for Electronic System Design, 2016, p. 101 - 112 (Lecture Notes in Electrical Enginieering)
ISBN: 978-3-319-24457-0
URL: https://www.springer.com/de/book/9783319244556
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Koch D., Hannig F., Ziener D. (ed.):
FPGAs for Software Programmers
Berlin; Heidelberg: 2016
ISBN: 978-3-319-26406-6
DOI: 10.1007/978-3-319-26408-0
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Koch D., Ziener D., Hannig F.:
FPGA versus Software Programming - Why, When, and How?
In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, 2016, p. 1-21
DOI: 10.1007/978-3-319-26408-0_1
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Lari V.:
Invasive Tightly Coupled Processor Arrays
In: Springer book series on Computer Architecture and Design Methodologies, Singapore: Springer, 2016
ISBN: 978-981-10-1058-3
DOI: 10.1007/978-981-10-1058-3
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Lari V., Weichslgartner A., Tanase AP., Witterauf M., Khosravi F., Teich J., Heißwolf J., Friederich S., Becker J.:
Providing Fault Tolerance Through Invasive Computing
In: it - Information Technology 58 (2016), p. 309-238
ISSN: 1611-2776
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Letras M., Hernández-León R., Cumplido R.:
Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning
2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
DOI: 10.1109/IPDPSW.2016.98
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Letras M., Morales-Reyes A., Cumplido R.:
A scalable and customizable processor array for implementing cellular genetic algorithms
In: Neurocomputing (2016), p. 899 - 910
ISSN: 0925-2312
DOI: 10.1016/j.neucom.2015.05.128
URL: http://www.sciencedirect.com/science/article/pii/S0925231215015933
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Membarth R., Reiche O., Hannig F., Teich J., Körner M., Eckert W.:
HIPAcc: A Domain-Specific Language and Compiler for Image Processing
In: IEEE Transactions on Parallel and Distributed Systems 27 (2016), p. 210-224
ISSN: 1045-9219
DOI: 10.1109/TPDS.2015.2394802
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Mitra T., Teich J., Thiele L. (ed.):
Adaptive Isolation for Predictability and Security
2016
(Dagstuhl Reports, Vol. 6)
BibTeX: Download
Navet N., Seyler J., Migge J.:
Timing Verification of Realtime Automotive Networks: What can we expect from Simulation?
8th European Congress on Embedded Real Time Software and Systems (ERTS) (Toulouse, 27. January 2016 - 29. January 2016)
In: Proceedings of the 8th European Congress on Embedded Real Time Software and Systems (ERTS) 2016
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Posewsky T., Ziener D.:
Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancún, 30. November 2016 - 2. December 2016)
In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) 2016
DOI: 10.1109/ReConFig.2016.7857167
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Pöppl A., Bader M., Schwarzer T., Glaß M.:
Simulating shallow water waves with lazy activation of patches using ActorX10
Second International Workshop on Extreme Scale Programming Models and Middleware (ESPM2)
In: Proceedings of the Second International Workshop on Extreme Scale Programming Models and Middleware (ESPM2) 2016
DOI: 10.1109/ESPM2.2016.9
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Roloff S., Hannig F., Teich J.:
InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip
Design, Automation and Test in Europe (DATE) (Dresden, 14. March 2016 - 18. March 2016)
In: Tool presentation at the University Booth 2016
URL: https://www.date-conference.com/system/files/file/date16/ubooth/37912.pdf
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Roloff S., Pöppl A., Schwarzer T., Wildermann S., Baader M., Glaß M., Hannig F., Teich J.:
ActorX10: An Actor Library for X10
ACM SIGPLAN X10 Workshop (X10), ACM (Santa Barbara, CA)
In: Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) 2016
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Rosales R., Herglotz C., Glaß M., Teich J., Kaup A.:
Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling
Architecture of Computing Systems (ARCS) (Nürnberg, 4. April 2016 - 7. April 2016)
In: Springer (ed.): In Proceedings of the International Conference on Architecture of Computing Systems (ARCS), Berlin; Heidelberg: 2016
DOI: 10.1007/978-3-319-30695-7_20
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Salcic Z., Nadeem M., Park H., Teich J.:
A heterogeneous multi-core SoC for mixed criticality industrial automation systems
Emerging Technologies and Factory Automation (ETFA)
In: Proceedings Emerging Technologies and Factory Automation (ETFA), 2016 IEEE 21st International Conference 2016
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Salcic Z., Nadeem M., Park H., Teich J.:
Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor
10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (Lyon, 21. September 2016 - 23. September 2016)
In: Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) 2016
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Schmid M., Reiche O., Hannig F., Teich J.:
HIPAcc
In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016
DOI: 10.1007/978-3-319-26408-0_12
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Schmid M., Schmitt C., Hannig F., Malazgirt GA., Sönmez N., Yurdakul A., Cristal A.:
Big Data and HPC Acceleration with Vivado HLS
In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016, p. 115-136
DOI: 10.1007/978-3-319-26408-0_7
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Schmitt C., Kuckuk S., Hannig F., Teich J., Köstler H., Rüde U., Lengauer C.:
Systems of Partial Differential Equations in ExaSlang
In: Software for Exascale Computing - SPPEXA 2013-2015, Berlin, Heidelberg, New York: Springer, 2016, p. 47-67 (Lecture Notes in Computational Science and Engineering, Vol.113)
ISBN: 9783319405261
DOI: 10.1007/978-3-319-40528-5_3
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Selgrad K., Lier A., Dörntlein J., Reiche O., Stamminger M.:
A High-Performance Image Processing DSL for Heterogeneous Architectures
9th European Lisp Symposium (Krakau, 9. May 2016 - 10. May 2016)
In: Proceedings of ELS 9th European Lisp Symposium 2016
URL: https://dl.acm.org/citation.cfm?id=3005729.3005734
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Smirnov F., Glaß M., Reimann F., Teich J.:
Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors
53nd ACM/EDAC/IEEE Design Automation Conference (DAC 2016) (Austin, 5. June 2016 - 9. June 2016)
In: Proceedings of the 53nd ACM/EDAC/IEEE Design Automation Conference (DAC 2016) 2016
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Streit FJ., Pantho MJH., Bobda C., Roullet C.:
Vision-Based Path Construction and Maintenance for Indoor Guidance of Autonomous Ground Vehicles Based on Collaborative Smart Cameras
International Conference on Distributed Smart Cameras (ICDSC) (Paris, France, 12. September 2017 - 15. September 2017)
In: ACM Proceedings of the 10th International Conference on Distributed Smart Cameras 2016
DOI: 10.1145/2967413.2967425
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Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
LoopInvader: A Compiler for Tightly Coupled Processor Arrays
Design, Automation and Test in Europe (DATE) (Dresden, 14. March 2016 - 18. March 2016)
In: Tool presentation at the University Booth 2016
URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
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Teich J.:
Invasive Computing - Editorial
In: it - Information Technology 58 (2016), p. 263-265
ISSN: 1611-2776
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Teich J., Glaß M., Roloff S., Schröder-Preikschat W., Snelting G., Weichslgartner A., Wildermann S.:
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing
10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (Lyon, 21. September 2016 - 23. September 2016)
In: Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) 2016
DOI: 10.1109/MCSoC.2016.30
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Wang B., Xu Y., Hasholzner R., Drewes C., Rosales R., Graf S., Falk J., Glaß M., Teich J.:
Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design
19. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2016) (Freiburg, 1. March 2016 - 2. March 2016)
In: In Proceedings of the 19. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2016) 2016
DOI: 10.6094/UNIFR/10643
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Weichslgartner A., Teich J.:
Position Paper: Towards Redundant Communication through Hybrid Application Mapping
Third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Nuremberg, 4. April 2016 - 5. April 2016)
In: Proceedings of the third International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2016
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Weichslgartner A., Wildermann S., Götzfried J., Freiling F., Glaß M., Teich J.:
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs
19th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (St. Goar, 23. May 2016 - 25. May 2016)
In: In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2016
DOI: 10.1145/2906363.2906370
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Wildermann S., Bader M., Bauer L., Damschen M., Gabriel D., Gerndt M., Glaß M., Henkel J., Paul J., Pöppl A., Roloff S., Schwarzer T., Snelting G., Stechele W., Teich J., Weichslgartner A., Zwinkau A.:
Invasive Computing for Timing-Predictable Stream Processing on MPSoCs
In: it - Information Technology 58 (2016), p. 267-280
ISSN: 1611-2776
DOI: 10.1515/itit-2016-0021
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Wille R., Keszocze O., Walter M., Rohrs P., Chattopadhyay A., Drechsler R.:
Look-Ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
DOI: 10.1109/ASPDAC.2016.7428026
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Witterauf M., Tanase AP., Hannig F., Teich J.:
Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (London, 6. July 2016 - 8. July 2016)
In: Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016
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Xu Y., Teich J.:
Hierarchical Statistical Leakage Analysis and its Application
In: ACM Transactions on Design Automation of Electronic Systems (2016)
ISSN: 1084-4309
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Ziener D., Weber H., Vogt JS., Schürfeld U., Meyer-Wegener K., Teich J., Dennl C., Becher A., Bauer F.:
FPGA-Based Dynamically Reconfigurable SQL Query Processing
In: ACM Transactions on Reconfigurable Technology and Systems 9 (2016), p. 25:1-25:24
ISSN: 1936-7406
DOI: 10.1145/2845087
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Özkan MA., Reiche O., Hannig F., Teich J.:
FPGA-Based Accelerator Design from a Domain-Specific Language
26th International Conference on Field-Programmable Logic and Applications (FPL) (Lausanne, 29. August 2016 - 2. September 2016)
In: Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL) 2016
DOI: 10.1109/FPL.2016.7577357
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Aliee H., Borgonovo E., Glaß M., Teich J.:
Importance measures in time-dependent reliability analysis and system design
25th European Safety and Reliability Conference, ESREL 2015 (Zürich, 7. September 2015 - 10. September 2015)
In: Proceedings of the Annual European Safety and Reliability Conference (ESREL '15) 2015
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84959018237&origin=inward
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Aliee H., Glaß M., Chen L., Ebrahimi M., Khosravi F., Kleeberger VB., Listl A., Müller-Gritschneder D., Oboril F., Schlichtmann U., Tahoori MB., Teich J., Wehn N., Weis C.:
Application-aware cross-layer reliability analysis and optimization
In: it - Information Technology 57 (2015), p. 159-169
ISSN: 1611-2776
DOI: 10.1515/itit-2014-1080
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Becher A., Echavarria Gutiérrez JA., Ziener D., Teich J.:
Approximate Adder Structures on FPGAs
AxC15: 1st Workshop on Approximate Computing (Paderborn, Germany)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Approximate_Adder_Structures_on_FPGAs.pdf
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Becher A., Ziener D., Meyer-Wegener K., Teich J.:
A co-design approach for accelerated SQL query processing via FPGA-based data filtering
International Conference on Field Programmable Technology, FPT 2015 (Queenstown, 7. December 2015 - 9. December 2015)
DOI: 10.1109/FPT.2015.7393148
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Biglari M., Barijough KM., Goudarzi M., Pourmohseni B.:
A Fine-Grained Configurable Cache Architecture for Soft Processors
International Symposium on Computer Architecture and Digital Systems (CADS) (Tehran, 7. October 2015 - 8. October 2015)
In: Proceedings of the 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) 2015
DOI: 10.1109/CADS.2015.7377783
URL: https://ieeexplore.ieee.org/document/7377783/
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Boppu S.:
Code Generation for Tightly Coupled Processor Arrays (Dissertation, 2015)
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Falk J.:
A Clustering-Based MPSoC Design Flow for Data Flow-Oriented Applications (Dissertation, 2015)
DOI: 10.13140/RG.2.1.5029.5763
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Falk J., Schwarzer T., Glaß M., Teich J., Zebelein C., Haubelt C.:
Quasi-static scheduling of data flow graphs in the presence of limited channel capacities
13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015
DOI: 10.1109/ESTIMedia.2015.7351766
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Falk J., Schwarzer T., Zhang L., Glaß M., Teich J.:
Automatic communication-driven virtual prototyping and design for networked embedded systems
In: Microprocessors and Microsystems 39 (2015), p. 1012–1028
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2015.08.008
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Gangadharan D., Sousa É., Lari V., Hannig F., Teich J.:
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms
48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (Pacific Grove, CA, 2. November 2014 - 5. November 2014)
In: Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) 2015
DOI: 10.1109/ACSSC.2014.7094471
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Glein R., Rittner F., Becher A., Ziener D., Frickel J., Teich J., Heuberger A.:
Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy
2015 NASA/ESA Conference on Adaptive Hardware and Systems (Montreal, 15. June 2015 - 18. June 2015)
In: IEEE (ed.): Proceedings of 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
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Graf S.:
Design and Optimization of Multi-Variant Automotive E/E Architecture Component Platforms (Dissertation, 2015)
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Graf S., Glaß M., Teich J.:
Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms
18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) (Chemnitz, 3. March 2015 - 4. March 2015)
In: Proceedings of 18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) 2015
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Graf S., Glaß M., Teich J., Platte D.:
A Methodology for the Optimized Design of an E/E Architecture Component Platform
Stuttgart International Symposium (Stuttgart, 17. March 2015 - 18. March 2015)
In: Proceedings of the Stuttgart International Symposium 2015
DOI: 10.1007/978-3-658-08844-6_14
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Graf S., Reinhart S., Glaß M., Teich J., Platte D.:
Robust Design of E/E Architecture Component Platforms
52nd ACM/EDAC/IEEE Design Automation Conference (DAC 2015) (San Francisco, CA, 7. June 2015 - 11. June 2015)
In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC 2015) 2015
DOI: 10.1145/2744769.2747941
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Hannig F., Fey D., Lokhmotov A. (ed.):
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
2015
Open Access: http://arxiv.org/abs/1502.07241
URL: http://arxiv.org/abs/1502.07241
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Hannig F., Herkersdorf A.:
Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures
In: Journal of Systems Architecture 61 (2015), p. 600
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.11.003
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Hannig F., Koch D., Ziener D. (ed.):
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
2015
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Heißwolf J., Weichslgartner A., Zaib A., Friederich S., Masing L., Stein C., Duden M., Klöpfer R., Teich J., Wild T., Herkersdorf A., Becker J.:
Fault-tolerant communication in invasive networks on chip
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) 2015
DOI: 10.1109/AHS.2015.7231156
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Khosravi F., Müller M., Glaß M., Teich J.:
Uncertainty-aware reliability analysis and optimization
2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (Grenoble, 9. March 2015 - 13. March 2015)
In: Proceedings of Design, Automation and Test in Europe (DATE 2015) 2015
DOI: 10.7873/DATE.2015.0319
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Kuckuk S., Schmitt C., Kronawitter S.:
ExaSlang and the ExaStencils Code Generator
PASC'15 (Zürich, 1. June 2015 - 3. June 2015)
BibTeX: Download
Lari V.:
Invasive Tightly Coupled Processor Arrays (Dissertation, 2015)
BibTeX: Download
Lari V., Tanase AP., Teich J., Witterauf M., Khosravi F., Hannig F., Meyer B.:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. June 2016 - 18. June 2015)
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
DOI: 10.1109/AHS.2015.7231157
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Morales-Reyes A., Escalante HJ., Letras M., Cumplido R.:
An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms
Annual Conference on Genetic and Evolutionary Computation - GECCO '15
DOI: 10.1145/2739480.2754699
URL: http://doi.acm.org/10.1145/2739480.2754699
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Mühlenthaler M.:
Degree-constrained Subgraph Reconfiguration is in P
40th International Symposium on Mathematical Foundations of Computer Science (MFCS) (Milano, 24. August 2015 - 28. August 2015)
In: Proceedings of the 40th International Symposium on Mathematical Foundations of Computer Science (MFCS) 2015
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Mühlenthaler M.:
Fairness in Academic Course Timetabling
Cham, Heidelberg, New York, Dordrecht, London: Springer International Publishing, 2015
(Lecture Notes in Economics and Mathematical Systems, Vol.678)
ISBN: 978-3-319-12798-9
DOI: 10.1007/978-3-319-12799-6
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Mühlenthaler M.:
Fairness in Academic Course Timetabling (Dissertation, 2015)
DOI: 10.1007/978-3-319-12799-6
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Paul J., Stechele W., Oechslein B., Erhardt C., Schedel J., Lohmann D., Schröder-Preikschat W., Kröhnert M., Asfour T., Sousa É., Hannig F., Lari V., Teich J., Grudnitsky A., Bauer L., Henkel J.:
Resource-awareness on heterogeneous MPSoCs for image processing
In: Journal of Systems Architecture 61 (2015), p. 668-680
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.09.002
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Raß A., Schmitt M., Wanka R.:
Explanation of Stagnation at Points that are not Local Optima in Particle Swarm Optimization by Potential Analysis
17th Genetic and Evolutionary Computation Conference (GECCO) (Madrid, Spain, 11. July 2015 - 15. July 2015)
In: ACM New York, NY, USA (ed.): Companion of Proc. 17th Genetic and Evolutionary Computation Conference (GECCO) 2015
DOI: 10.1145/2739482.2764654
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Raß A., Schmitt M., Wanka R.:
Explanation of Stagnation at Points that are not Local Optima in Particle Swarm Optimization by Potential Analysis [Extended Version]
(2015)
URL: https://arxiv.org/abs/1504.08241
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(online publication)
Reiche O., Häublein K., Reichenbach M., Hannig F., Teich J., Fey D.:
Automatic Optimization of Hardware Accelerators for Image Processing
DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (Grenoble, 13. March 2015 - 13. March 2015)
In: Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) 2015
URL: http://arxiv.org/abs/1502.07448
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Reiche O., Häublein K., Reichenbach M., Schmid M., Hannig F., Teich J., Fey D.:
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
In: Journal of Systems Architecture 61 (2015), p. 646-658
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.09.004
URL: https://www12.cs.fau.de/downloads/reiche/publications/RHRSHTF15.pdf
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Roloff S., Schafhauser D., Hannig F., Teich J.:
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 (San Francisco, CA, 7. June 2015 - 11. June 2015)
In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) 2015
DOI: 10.1145/2744769.2744840
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Roloff S., Wildermann S., Hannig F., Teich J.:
Invasive computing for predictable stream processing: A simulation-based case study
13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015 (Amsterdam, 8. October 2015 - 9. October 2015)
DOI: 10.1109/ESTIMedia.2015.7351761
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Schmid M.:
Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain (Dissertation, 2015)
BibTeX: Download
Schmid M., Reiche O., Hannig F., Teich J.:
Loop Coarsening in C-based High-Level Synthesis
26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Toronto, 27. July 2015 - 29. July 2015)
In: Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
DOI: 10.1109/ASAP.2015.7245730
URL: https://www12.cs.fau.de/downloads/reiche/publications/SRHT15.pdf
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Schmitt C., Schmid M., Hannig F., Teich J., Kuckuk S., Köstler H.:
Generation of Multigrid-based Numerical Solvers for FPGA Accelerators
2nd International Workshop on High-Performance Stencil Computations (HiStencils) (Amsterdam, 20. January 2015 - 20. January 2015)
In: Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils) 2015
URL: https://www12.cs.fau.de/downloads/schmittch/publications/SSHTKK15histencils.pdf
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Schmitt M.:
Convergence Analysis for Particle Swarm Optimization (Dissertation, 2015)
URL: https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-61621
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Schmitt M., Wanka R.:
Particle Swarm Optimization Almost Surely Finds Local Optima
In: Theoretical Computer Science 561A (2015), p. 57-72
ISSN: 0304-3975
DOI: 10.1016/j.tcs.2014.05.017
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Schmitt M., Wanka R., Schwab L.:
Multimodal Medical Image Registration Using Particle Swarm Optimization with Influence of the Data's Initial Orientation
12th IEEE Conf. on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB) (Niagara Falls)
In: Proc. 12th IEEE Conf. on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB) 2015
DOI: 10.1109/CIBCB.2015.7300314
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Schwarzer T., Falk J., Glaß M., Teich J., Zebelein C., Haubelt C.:
Throughput-optimizing compilation of dataflow applications for multi-cores using quasi-static scheduling
18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar)
In: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2015
DOI: 10.1145/2764967.2764972
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Seyler J., Navet N., Fejoz L., Teich J.:
Insights on the Configuration and Performances of SOME/IP Service Discovery
In: SAE International Journal of Passenger Cars - Electronic and Electrical Systems 8 (2015), p. 124-129
ISSN: 1946-4614
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Seyler J., Streichert T., Glaß M., Navet N., Teich J.:
Formal analysis of the startup delay of SOME/IP service discovery
2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (Grenoble, 9. March 2015 - 13. March 2015)
In: Proceedings of Design, Automation and Test in Europe (DATE 2015) 2015
DOI: 10.7873/DATE.2015.0469
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Sousa É., Hannig F., Teich J.:
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
International Embedded Systems Symposium (IESS) (Foz do Iguaçu, 3. November 2015 - 6. November 2015)
In: Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, and Achim Rettberg (ed.): Proceedings of the International Embedded Systems Symposium (IESS) 2015
DOI: 10.1007/978-3-319-90023-0
URL: http://www.springer.com/us/book/9783319900223
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Sousa É., Hannig F., Teich J., Schlichtmann U., Chen Q.:
Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar, 1. June 2015 - 3. June 2015)
In: In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2015
DOI: 10.1145/2764967.2771933
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Tanase AP., Witterauf M., Hannig F., Teich J.:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays
ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015 (Austin, 21. September 2015 - 23. September 2015)
In: Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2015
DOI: 10.1109/MEMCOD.2015.7340486
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Tanase AP., Witterauf M., Teich J., Hannig F., Lari V.:
On-demand fault-tolerant loop processing on massively parallel processor arrays
26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 (Toronto, 27. July 2015 - 29. July 2015)
In: In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
DOI: 10.1109/ASAP.2015.7245734
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Teich J.:
Adaptive Isolation for Predictable MPSoC Stream Processing
18th Int. Workshop on Software and Compilers for Embedded Systems (SCOPES 2015) (Schloss Rheinfels, St. Goar, 1. June 2015 - 3. June 2015)
In: Proc. of the 18th Int. Workshop on Software and Compilers for Embedded Systems (SCOPES 2015) 2015
DOI: 10.1145/2764967.2771821
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Teich J., Boppu S., Hannig F., Lari V.:
Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays
In: Luk, Wayne, Constantinides, George A. (ed.): Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015, p. 167-206
ISBN: 978-1-78326-696-8
DOI: 10.1142/9781783266975_0010
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Teich J., Lari V., Tanase AP., Witterauf M., Khosravi F., Meyer B.:
Techniques for on-demand structural redundancy for massively parallel processor arrays
In: Journal of Systems Architecture 61 (2015), p. 615-627
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.10.004
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Tobola A., Espig C., Streit FJ., Korpok O., Leutheuser H., Schmitz B., Hofmann C., Struck M., Weigand C., Eskofier B., Fischer G.:
Scalable ECG Hardware and Algorithms for Extended Runtime of Wearable Sensors
IEEE International Symposium on Medical Measurements and Applications (MeMeA) (Torino)
In: 2015 IEEE International Symposium on Medical Measurements and Applications 2015
DOI: 10.1109/MeMeA.2015.7145209
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Tobola A., Streit FJ., Espig C., Korpok O., Leutheuser H., Sauter C., Lang N., Schmitz B., Hofmann C., Struck M., Weigand C., Eskofier B., Fischer G.:
Sampling rate impact on energy consumption of biomedical signal processing systems
12th International Conference on Wearable and Implantable Body Sensor Networks (BSN) (Cambridge, USA, 9. June 2015 - 12. June 2015)
DOI: 10.1109/BSN.2015.7299392
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Weichslgartner A., Heißwolf J., Zaib A., Wild T., Herkersdorf A., Becker J., Teich J.:
Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures.
International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Porto, 24. March 2015 - 24. March 2015)
In: Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2015
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Wildermann S., Weichslgartner A., Teich J.:
Design Methodology and Run-Time Management for Predictable Many-Core Systems
18th IEEE International Symposium on Real-Time Distributed Computing Workshops, ISORCW 2015 (Auckland)
In: Proceedings of the 6th IEEE Workshop on Self-Organizing Real-Time Systems (SORT 2015) 2015
DOI: 10.1109/ISORCW.2015.48
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Witterauf M., Tanase AP., Hannig F., Teich J.:
Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing
11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 12. July 2015 - 18. July 2015)
In: Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) 2015
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Witterauf M., Tanase AP., Teich J., Lari V., Zwinkau A., Snelting G.:
Adaptive fault tolerance through invasive computing
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. June 2016 - 18. June 2015)
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
DOI: 10.1109/AHS.2015.7231155
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Xu Y.:
System-Level Power and Performance Estimation in Early SoC Design Phases (Dissertation, 2015)
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Zaib A., Heißwolf J., Weichslgartner A., Wild T., Teich J., Becker J., Herkersdorf A.:
Network interface with task spawning support for NoC-based DSM architectures
28th International Conference on Architecture of Computing Systems, ARCS 2015 (Porto, 24. March 2015 - 24. March 2015)
In: Proceedings of 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS) 2015
DOI: 10.1007/978-3-319-16086-3_15
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Zhang L., Glaß M., Ballmann N., Teich J.:
Bridging Algorithm and ESL Design: MATLAB/Simulink Model Transformation and Validation
In: Marie-Minerve Louërat, Torsten Maehne (ed.): Languages, Design Methods, and Tools for Electronic System Design, Springer, 2015, p. 189-206
ISBN: 978-3-319-06316-4
DOI: 10.1007/978-3-319-06317-1_10
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Ziener D., Bauer F., Becher A., Dennl C., Meyer-Wegener K., Schürfeld U., Teich J., Vogt JS., Weber H.:
FPGA-Based Dynamically Reconfigurable SQL Query Processing
In: ACM Transactions on Reconfigurable Technology and Systems (2015)
ISSN: 1936-7406
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Abelein U., Cook A., Engelke P., Glaß M., Reimann F., Gómez LR., Russ T., Teich J., Ull D., Wunderlich HJ.:
Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures
Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
In: Proc. of Design, Automation and Test in Europe (DATE), New York, NY, USA: 2014
DOI: 10.7873/DATE2014.373
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Aliee H., Glaß M., Khosravi F., Teich J.:
An efficient technique for computing importance measures in automatic design of dependable embedded systems
2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014 (New Delhi, 12. October 2014 - 17. October 2014)
In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014) 2014
DOI: 10.1145/2656075.2656079
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Aliee H., Glaß M., Wanka R., Teich J.:
Automatic Graph-based Success Tree Construction and Analysis
Annual Reliability and Maintainability Symposium (RAMS) (Colorado Springs, Colorado, USA, 27. January 2014 - 30. January 2014)
In: Proc. 60th Annual Reliability and Maintainability Symposium (RAMS) 2014
DOI: 10.1109/RAMS.2014.6798487
URL: https://www12.informatik.uni-erlangen.de/people/rwanka/publications/AGWT14.php
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Bassimir B., Schmitt M., Wanka R.:
How Much Forcing is Necessary to Let the Results of Particle Swarms Converge?
International Conference on Swarm Intelligence Based Optimization (ICSIBO)
In: Proc. Int. Conf. on Swarm Intelligence Based Optimization (ICSIBO) 2014
DOI: 10.1007/978-3-319-12970-9_11
URL: http://www12.cs.fau.de/people/rwanka/publications/BSW14.php
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Becher A., Bauer F., Ziener D., Teich J.:
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration
24th International Conference on Field Programmable Logic and Applications, FPL 2014 (Munich, 2. September 2014 - 4. September 2014)
In: Proceedings of the Conference on Field-Programmable Logic and Applications (FPL 2014) 2014
DOI: 10.1109/FPL.2014.6927502
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Boppu S., Hannig F., Teich J.:
Compact Code Generation for Tightly-Coupled Processor Arrays
In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 77(1-2) (2014), p. 5-29
ISSN: 1387-5485
DOI: 10.1007/s11265-014-0891-2
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Echavarria Gutiérrez JA., Morales-Reyes A., Cumplido R., Salido MA.:
FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (Cancun, 8. December 2014 - 10. December 2014)
In: Proceedings of 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2014
DOI: 10.1109/ReConFig.2014.7032525
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Gangadharan D., Tanase AP., Hannig F., Teich J.:
Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays
DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES) (Dresden, Germany, 28. March 2014 - 28. March 2014)
URL: https://ecsi.org/resource/workshop/2014/3PMCES/DATE/paper/timing-analysis-heterogeneous-architecture-massively-parallel-processor-arrays
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Gangadharan D., Teich J., Chakraborty S.:
Quality-aware video decoding on thermally-constrained MPSoC platforms
25th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014 (Zurich, 18. June 2014 - 29. June 2014)
In: Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2014
DOI: 10.1109/ASAP.2014.6868670
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Glaß M., Graf S., Reimann F., Teich J.:
Design and Evaluation of Future Ethernet AVB-based ECU Networks
In: Embedded Systems Development, From Functional Models to Implementations 2014, Berlin; Heidelberg: Springer-Verlag, 2014, p. 205-220
ISBN: 978-1-4614-3878-6
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Glein R., Schmidt B., Rittner F., Teich J., Ziener D.:
A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor
22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014 (Boston, 11. May 2014 - 13. May 2014)
In: Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014) 2014
DOI: 10.1109/FCCM.2014.79
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Glocker E., Boppu S., Chen Q., Schlichtmann U., Teich J., Schmitt-Landsiedel D.:
Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)
In: Advances in Radio Science 12 (2014), p. 103-109
ISSN: 1684-9973
DOI: 10.5194/ars-12-103-2014
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Graf S., Glaß M., Teich J., Lauer C.:
Design Space Exploration for Automotive E/E Architecture Component Platforms
Euromicro Conference on Digital System Design (DSD) (Verona, 27. August 2014 - 29. August 2014)
In: Proc. of Euromicro Conference on Digital System Design (DSD), New York, NY, USA: 2014
DOI: 10.1109/DSD.2014.43
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Graf S., Glaß M., Teich J., Lauer C.:
Multi-Variant-based Design Space Exploration for Automotive Embedded Systems
Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
In: Proc. of Design, Automation and Test in Europe (DATE), New York, NY, USA: 2014
DOI: 10.7873/DATE2014.020
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Graf S., Reimann F., Glaß M., Teich J.:
Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (New Delhi, 12. October 2014 - 17. October 2014)
In: Proc. of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA: 2014
DOI: 10.1145/2656075.2656102
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Grebhahn A., Kuckuk S., Schmitt C., Köstler H., Siegmund N., Apel S., Hannig F., Teich J.:
Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror
In: Parallel Processing Letters 24 (2014)
ISSN: 0129-6264
DOI: 10.1142/S0129626414410011
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Grebhahn A., Siegmund N., Apel S., Kuckuk S., Schmitt C.:
Optimizing the Performance of Customizable Stencil Codes with Feature-Interaction Detection
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Grebhahn A., Siegmund N., Apel S., Kuckuk S., Schmitt C., Köstler H.:
Optimizing Performance of Stencil Code with SPL Conqueror
1st International Workshop on High-Performance Stencil Computations (HiStencils) (Vienna, 20. January 2014 - 20. January 2014)
In: Proceedings of the 1st International Workshop on High-Performance Stencil Computations (HiStencils) 2014
URL: https://www12.cs.fau.de/downloads/schmittch/publications/GSAKSK14histencils.pdf
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Hannig F., Koch D., Ziener D. (ed.):
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
2014
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Hannig F., Lari V., Boppu S., Tanase AP., Reiche O.:
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach
In: ACM Transactions on Embedded Computing Systems 13 (2014), p. 133:1-133:29
ISSN: 1539-9087
DOI: 10.1145/2584660
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Hannig F., Teich J. (ed.):
Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014)
2014
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Heisswolf J., Zaib A., Zwinkau A., Kobbe S., Weichslgartner A., Teich J., Henkel J., Snelting G., Herkersdorf A., Becker J.:
CAP: Communication Aware Programming
The 51st Annual Design Automation Conference (DAC) (San Francisco, CA, 2. June 2014 - 5. June 2014)
In: Proc. of The 51st Annual Design Automation Conference (DAC), New York, NY, USA: 2014
DOI: 10.1145/2593069.2593103
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Herkersdorf A., Aliee H., Engel M., Glaß M., Gimmler-Dumont C., Henkel J., Kleeberger VB., Kochte MA., Kühn JM., Mueller-Gritschneder D., Nassif SR., Rauchfuss H., Rosenstiel W., Schlichtmann U., Shafique M., Tahoori MB., Teich J., Wehn N., Weis C., Wunderlich HJ.:
Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-Chip Resilience
In: Microelectronics Reliability 54 (2014), p. 1066-1074
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2013.12.012
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Keszocze O., Wille R., Ho TY., Drechsler R.:
Exact One-Pass Synthesis of Digital Microfluidic Biochips
51st Annual Design Automation Conference, DAC 2014 (San Francisco, CA)
DOI: 10.1145/2593069.2593135
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Khosravi F., Reimann F., Glaß M., Teich J.:
Multi-objective local-search optimization using reliability importance measuring
51st Annual Design Automation Conference, DAC 2014 (San Francisco, CA, 1. June 2014 - 5. June 2014)
In: Proceedings of the 51st Design Automation Conference (DAC 2014) 2014
DOI: 10.1145/2593069.2593164
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Kuckuk S., Schmitt C., Köstler H., Hannig F., Teich J.:
Generating Highly Parallel Geometric Multigrid Solvers with the ExaStencils Apporach
3rd Workshop on Extreme-scale Programming Tools (New Orleans, 17. November 2014 - 17. November 2014)
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Lange V., Schmitt M., Wanka R.:
Towards a Better Understanding of the Local Attractor in Particle Swarm Optimization: Speed and Solution Quality
International Conference on Adaptive and Intelligent Systems (ICAIS) (Bournemouth, UK, 8. September 2014 - 10. September 2014)
In: Proc. International Conference on Adaptive and Intelligent Systems (ICAIS) 2014
DOI: 10.1007/978-3-319-11298-5_10
URL: https://www12.informatik.uni-erlangen.de/people/rwanka/publications/LSW14.php
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Lari V., Tanase AP., Hannig F., Teich J.:
Massively Parallel Processor Architectures for Resource-aware Computing
First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing ) (Paderborn, 29. May 2014 - 30. May 2014)
In: Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) 2014
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Lengauer C., Apel S., Bolten M., Größlinger A., Hannig F., Köstler H., Rüde U., Teich J., Grebhahn A., Kronawitter S., Kuckuk S., Rittich H., Schmitt C.:
ExaStencils: Advanced Stencil-Code Engineering - First Project Report
(2014)
Open Access: http://www.fim.uni-passau.de/fileadmin/files/forschung/mip-berichte/MIP1401.pdf
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(Techreport)
Lengauer C., Apel S., Größlinger A., Grebhahn A., Kronawitter S., Bolten M., Rittich H., Hannig F., Köstler H., Rüde U., Teich J., Kuckuk S., Schmitt C.:
ExaStencils: Advanced Stencil-Code Engineering
Euro-Par: Parallel Processing Workshops (Porto, 25. August 2014 - 26. August 2014)
In: Proceedings of Euro-Par 2014: Parallel Processing Workshops, Berlin; Heidelberg: 2014
DOI: 10.1007/978-3-319-14313-2_47
URL: http://link.springer.com/content/pdf/10.1007/978-3-319-14313-2_47.pdf
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Lukasiewycz M., Glaß M., Teich J., Chakraborty S.:
Exploration of Distributed Automotive Systems using Compositional Timing Analysis
In: Embedded Systems Development: From Functional Models to Implementations, Berlin; Heidelberg: Springer-Verlag, 2014, p. 189-204
ISBN: 978-1-4614-3878-6
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Membarth R., Reiche O., Hannig F., Teich J.:
Code Generation for Embedded Heterogeneous Architectures on Android
Conference on Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2014
DOI: 10.7873/DATE2014.099
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Membarth R., Reiche O., Schmitt C., Hannig F., Teich J., Stürmer M., Köstler H.:
Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language
In: Journal of Parallel and Distributed Computing 74 (2014), p. 3191-3201
ISSN: 0743-7315
DOI: 10.1016/j.jpdc.2014.08.008
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Mühlenthaler M., Wanka R.:
Fairness in Academic Course Timetabling
In: Annals of Operations Research (2014)
ISSN: 0254-5330
DOI: 10.1007/s10479-014-1553-2
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Mühlenthaler M., Wanka R.:
The Connectedness of Clash-free Timetables
Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT) (York, UK)
In: Proc. 10th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT) 2014
URL: http://www12.cs.fau.de/people/rwanka/publications/MW14.php
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Narayanan V., Teich J.:
Introduction to the special issue on domain-specific multicore computing
In: Transactions on Embedded Computing Systems 13 (2014), Article No.: 129
ISSN: 1558-3465
DOI: 10.1145/2588609
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Paul J., Stechele W., Sousa É., Lari V., Hannig F., Teich J., Kröhnert M., Asfour T.:
Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 8. October 2014 - 10. October 2014)
In: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Gières, France: 2014
DOI: 10.1109/DASIP.2014.7115616
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Reiche O., Schmid M., Hannig F., Membarth R., Teich J.:
Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (New Dehli, 12. October 2014 - 17. October 2014)
In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA: 2014
DOI: 10.1145/2656075.2656081
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Reimann F., Glaß M., Teich J., Cook A., Gomez LR., Ull D., Wunderlich HJ., Engelke P., Abelein U.:
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures
The 51st Annual Design Automation Conference (DAC) (San Francisco, CA, 2. June 2014 - 5. June 2014)
In: Proc. of The 51st Annual Design Automation Conference (DAC), New York, NY, USA: 2014
DOI: 10.1145/2593069.2602971
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Roloff S., Hannig F., Teich J.:
Towards Actor-oriented Programming on PGAS-based Multicore Architectures
First International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Lübeck)
In: Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2014
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Rosales R., Glaß M., Teich J.:
Mahler: Sketch-based Model-driven Virtual Prototyping
In: Proc. of the 27th International Conference on Architecture of Computing Systems (ARCS), New York, NY, USA: IEEE Press, 2014, p. 85-97 (Lecture Notes in Computer Science, Vol.8350)
ISBN: 978-3-319-04890-1
DOI: 10.1007/978-3-319-04891-8_8
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Rosales R., Glaß M., Teich J., Wang B., Xu Y., Hasholzner R.:
MAESTRO - Holistic Actor-oriented Modeling of Non-Functional Properties and Firmware Behavior for MPSoCs
In: ACM Transactions on Design Automation of Electronic Systems 19 (2014), p. 23:1-23:26
ISSN: 1084-4309
DOI: 10.1145/2594481
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Schlichtmann U., Kleeberger VB., Abraham JA., Evans A., Gimmler-Dumon C., Glaß M., Herkersdorf A., Nassif SR., Wehn N.:
Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test
Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
In: Proc. of Design, Automation and Test in Europe (DATE), New York, NY, USA: 2014
DOI: 10.7873/DATE2014.265
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Schmid M., Apelt N., Hannig F., Teich J.:
An Image Processing Library for C-based High-Level Synthesis
Field-Programmable Logic and Applications (FPL) (Munich, 1. September 2014 - 5. September 2014)
In: Proc. of Field-Programmable Logic and Applications (FPL), New York, NY, USA: 2014
DOI: 10.1109/FPL.2014.6927424
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Schmid M., Hannig F., Tanase AP., Teich J.:
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model
In: Parallel Computing: Accelerating Computational Science and Engineering (CSE), Amsterdam, The Netherlands: IOS Press, 2014, p. 497-506 (Advances in Parallel Computing, Vol.25)
ISBN: 978-1-61499-380-3
DOI: 10.3233/978-1-61499-381-0-497
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Schmid M., Reiche O., Schmitt C., Hannig F., Teich J.:
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
First International Workshop on FPGAs for Software Programmers (FSP) (Munich, 1. September 2014 - 1. September 2014)
In: Proc. of the First International Workshop on FPGAs for Software Programmers (FSP) 2014
URL: http://arxiv.org/abs/1408.4721
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Schmid M., Tanase AP., Hannig F., Teich J., Bhadouria VS., Ghoshal D.:
Domain-Specific Augmentations for High-Level Synthesis
25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Zurich, 18. June 2014 - 20. June 2014)
In: Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, NY, USA: 2014
DOI: 10.1109/ASAP.2014.6868653
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Schmidt B., Ziener D., Teich J.:
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques
2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14 (Monterey, CA, 26. February 2014 - 28. February 2014)
In: In Proceedings of 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14 2014
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Schmidt B., Ziener D., Teich J.:
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning
Reconfigurable Architectures Workshop (RAW) (Phoenix, 19. May 2014 - 23. May 2014)
In: Proc. of the Reconfigurable Architectures Workshop (RAW) 2014
DOI: 10.1109/IPDPSW.2014.41
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Schmitt C., Kuckuk S., Hannig F., Köstler H., Teich J.:
ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers
4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (New Orleans, LA, USA, 17. November 2014 - 17. November 2014)
In: Proc. of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), New York, NY, USA: 2014
DOI: 10.1109/WOLFHPC.2014.11
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Schmitt C., Kuckuk S., Köstler H., Hannig F., Teich J.:
An Evaluation of Domain-Specific Language Technologies for Code Generation
14th International Conference on Computational Science and its Applications (ICCSA) (Minho, Guimaraes, 30. June 2014 - 3. July 2014)
In: Proc. of the 14th International Conference on Computational Science and its Applications (ICCSA), New York, NY, USA: 2014
DOI: 10.1109/ICCSA.2014.16
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Seyler J., Rahimov S., Streichert T., Glaß M., Teich J.:
DPSK modulated wakeup mechanism for point-to-point networks with partial network support
9th IEEE International Symposium on Industrial Embedded Systems, SIES 2014 (Pisa)
In: Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES) 2014
DOI: 10.1109/SIES.2014.6871209
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Seyler JR., Streichert T., Warkentin J., Spägele M., Glaß M., Teich J.:
A self-propagating wakeup mechanism for point-to-point networks with partial network support
17th Design, Automation and Test in Europe, DATE 2014 (Dresden, 24. March 2014 - 28. March 2014)
In: Proceedings of Design, Automation and Test in Europe (DATE 2014) 2014
DOI: 10.7873/DATE2014.019
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Sousa É., Gangadharan D., Hannig F., Teich J.:
Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures
17th Euromicro Conference on Digital System Design, DSD 2014 (Verona, 27. August 2014 - 29. August 2014)
In: Proceedings of the EUROMICRO Digital System Design Conference (DSD) 2014
DOI: 10.1109/DSD.2014.105
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Sousa É., Paul J., Lari V., Hannig F., Teich J., Stechele W.:
Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture.
Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. December 2017)
In: Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) 2014
Open Access: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
URL: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
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Tanase AP., Witterauf M., Teich J., Hannig F.:
Symbolic inner loop parallelisation for massively parallel processor arrays
12th ACM/IEEE International Conference on Methods and Models for System Design, MEMOCODE 2014 (Lausanne, 19. October 2014 - 21. October 2014)
In: Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2014
DOI: 10.1109/MEMCOD.2014.6961865
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Tate A., Kamil A., Dubey A., Größlinger A., Chamberlain B., Goglin B., Edwards CH., Newburn C., Padua D., Unat D., Jeannot E., Hannig F., Gysi T., Ltaief H., Sexton J., Labarta J., Shalf J., Fürlinger K., O’Brien K., Linardakis L., Besta M., Sawley MC., Abraham M., Bianco M., Pericàs M., Maruyama N., Kelly PHJ., Messmer P., Ross RB., Cledat R., Matsuoka S., Schulthess T., Hoefler T., Leung VJ.:
White Paper: Programming Abstractions for Data Locality
PADAL Workshop 2014 (Swiss National Supercomputing Center (CSCS), Lugano, Switzerland, 28. April 2014 - 29. April 2014)
In: Proc. of PADAL Workshop 2014
URL: http://www.padalworkshop.org/white-paper/
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Teich J., Tanase AP., Hannig F.:
Symbolic Mapping of Loop Programs onto Processor Arrays
In: Journal of Signal Processing Systems, Berlin; Heidelberg: Springer-Verlag, 2014, p. 31-59
DOI: 10.1007/s11265-014-0905-0
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Wang B., Xu Y., Rosales R., Hasholzner R., Glaß M., Teich J.:
End-to-End Power Estimation for Heterogeneous Cellular LTE SoCs in Early Design Phases
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (Palma de Mallorca, 29. September 2014 - 1. October 2014)
In: Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2014
DOI: 10.1109/PATMOS.2014.6951904
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Weichslgartner A., Gangadharan D., Wildermann S., Glaß M., Teich J.:
DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems
2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014 (New Delhi, 12. October 2014 - 17. October 2014)
In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014) 2014
DOI: 10.1145/2656075.2656083
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Weichslgartner A., Teich J.:
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure
First International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Lübeck)
In: Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2014
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Wildermann S., Glaß M., Teich J.:
Multi-Objective Distributed Run-time Resource Management for Many-Cores
Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
In: Proc. of Design, Automation and Test in Europe (DATE), New York, NY, USA: 2014
DOI: 10.7873/DATE2014.234
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Wildermann S., Teich J.:
Self-Integration for Virtualization of Embedded Many-Core Systems
Workshop on Self-Improving System Integration (SISSY 2014) (London, 8. September 2014 - 8. September 2014)
In: Proceedings of the Workshop on Self-Improving System Integration (SISSY 2014) 2014
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Xu Y., Wang B., Teich J.:
Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (Palma de Mallorca, 29. September 2014 - 1. October 2014)
In: Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2014
DOI: 10.1109/PATMOS.2014.6951860
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Zebelein C., Haubelt C., Falk J., Schwarzer T., Teich J.:
Model-based actor multiplexing with application to complex communication protocols
17th Design, Automation and Test in Europe, DATE 2014 (Dresden, 24. March 2014 - 28. March 2014)
In: Proceedings of Design, Automation and Test in Europe (DATE 2014) 2014
DOI: 10.7873/DATE2014.229
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Zhang L., Falk J., Schwarzer T., Glaß M., Teich J.:
Communication-driven Automatic Virtual Prototyping for Networked Embedded Systems
Euromicro Conference on Digital System Design (DSD) (Verona, 27. August 2014 - 29. August 2014)
In: Proc. of Euromicro Conference on Digital System Design (DSD), New York, NY, USA: 2014
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Aliee H., Glaß M., Reimann F., Teich J.:
Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults
Design, Automation and Test in Europe (DATE) (Grenoble, 18. March 2013 - 22. March 2013)
In: Proc. Design, Automation and Test in Europe, New York, NY, USA: 2013
DOI: 10.7873/DATE.2013.329
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Andres B., Gebser M., Schaub T., Haubelt C., Reimann F., Glaß M.:
Symbolic system synthesis using answer set programming
12th International Conference on Logic Programming and Nonmonotonic Reasoning, LPNMR 2013 (Corunna, 15. September 2013 - 19. September 2013)
In: Proceedings of the 12th International Conference on Logic Programming and Nonmonotonic Reasoning (LPNMR) 2013
DOI: 10.1007/978-3-642-40564-8_9
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Andres B., Schaub T., Gebser M., Haubelt C., Reimann F., Glaß M.:
A Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (Rostock, 12. March 2013 - 14. March 2013)
In: Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2013
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Angermeier J.:
Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computer (Dissertation, 2013)
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Biglari M., Qasemi E., Pourmohseni B.:
Maestro: A High Performance AES Encryption/Decryption System
International Symposium on Computer Architecture and Digital Systems (CADS) (Tehran, 30. October 2013 - 31. October 2013)
In: Proceedings of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) 2013
DOI: 10.1109/CADS.2013.6714255
URL: https://ieeexplore.ieee.org/document/6714255/
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Boppu S., Hannig F., Teich J.:
Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567544
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Boppu S., Lari V., Hannig F., Teich J.:
Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
Synopsys Users Group Conference (SNUG) (Munich, 14. May 2013 - 14. May 2013)
In: Proc. Synopsys Users Group Conference 2013
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Dennl C., Ziener D., Teich J.:
Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration
IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (Seattle, 28. April 2013 - 30. April 2013)
In: Proc. IEEE International Field-Programmable Custom Computing Machines Symposium 2013
DOI: 10.1109/FCCM.2013.38
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Falk J., Haubelt C., Teich J.:
Integrated Modeling Using Finite State Machines and Dataflow Graphs
In: huvra S. Bhattacharyya and Ed F. Deprettere and Rainer Leupers and Jarmo Takala (ed.): Handbook of Signal Processing Systems, 2013, p. 975-2013
DOI: 10.1007/978-1-4614-6859-2_30
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Falk J., Haubelt C., Zebelein C., Teich J.:
Integrated Modeling Using Finite State Machines and Dataflow Graphs
In: Bhattacharyya S., Deprettere E., Leupers R., Takala J. (ed.): Handbook of Signal Processing Systems, New York, NY: Springer, 2013
ISBN: 978-1-4614-6858-5
DOI: 10.1007/978-1-4614-6859-2_30
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Falk J., Zebelein C., Haubelt C., Teich J.:
A Rule-Based Quasi-Static Scheduling Approach for Static Islands in Dynamic Dataflow Graphs
In: ACM Transactions on Embedded Computing Systems, New York, NY: ACM, 2013, p. 74:1-74:31
DOI: 10.1145/2442116.2442124
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Falk J., Zebelein C., Haubelt C., Teich J.:
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
In: ACM Transactions on Embedded Computing Systems 12 (2013), Article No.: 74
ISSN: 1539-9087
DOI: 10.1145/2442116.2442124
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Gladigau J.:
Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling (Dissertation, 2013)
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Glock S., Rosales R., Reutelhuber F., Glaß M., Teich J., Fischer G., Weigel R., Ußmüller T.:
Scenario-Based Energy Estimation of Heterogeneous Integrated Systems at System Level
43rd European Microwave Conference (EuMC) (Nuremberg, 7. October 2013 - 10. October 2013)
In: Proc. 43rd European Microwave Conference 2013
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Graf S., Glaß M., Teich J.:
Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (Warnemünde, 12. March 2013 - 14. March 2013)
In: Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Rostock: 2013
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Graf S., Glaß M., Wintermann D., Teich J., Lauer C.:
IVaM: Implicit Variant Modeling and Management for Automotive Embedded Systems
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Montreal, QC, 29. September 2013 - 4. October 2013)
In: Proc. International Conference on Hardware/Software Codesign and System Synthesis, New York, NY, USA: 2013
DOI: 10.1109/CODES-ISSS.2013.6658982
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Hannig F., Schmid M., Lari V., Boppu S., Teich J.:
System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures
ACM International Conference on Computing Frontiers (CF) (Ischia, 14. May 2013 - 16. May 2013)
In: Proc. ACM International Conference on Computing Frontiers, New York, NY, USA: 2013
DOI: 10.1145/2482767.2482770
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Heisswolf J., Weichslgartner A., Zaib A., König R., Wild T., Herkersdorf A., Teich J., Becker J.:
Hardware Supported Adaptive Data Collection for Networks on Chip
IEEE 27th International Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW) (Boston, Massachusetts, 20. May 2013 - 24. May 2013)
In: Proc. IEEE 27th International Parallel and Distributed Processing Symposium Workshops PhD Forum, Red Hook, NY, USA: 2013
DOI: 10.1109/IPDPSW.2013.124
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Heisswolf J., Zaib A., Weichslgartner A., König R., Wild T., Teich J., Herkersdorf A., Becker J.:
Virtual Networks - Distributed Communication Resource Management
In: ACM Transactions on Reconfigurable Technology and Systems 6 (2013), p. 8:1-8:14
ISSN: 1936-7406
DOI: 10.1145/2492186
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Henkel J., Narayanan V., Parameswaran S., Teich J.:
Run-time adaption for highly-complex multi-core systems
11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013 (Montreal, QC, 29. September 2013 - 4. October 2013)
DOI: 10.1109/CODES-ISSS.2013.6659000
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Herkersdorf A., Engel M., Glaß M., Henkel J., Kleeberger VB., Kochte MA., Kühn JM., Nassif SR., Rauchfuss H., Rosenstiel W., Schlichtmann U., Shafique M., Tahoori MB., Teich J., Wehn N., Weis C., Wunderlich HJ.:
Cross-Layer Dependability Modeling and Abstraction in System on Chip
9th Workshop on Silicon Errors in Logic - System Effects (SELSE) (Palo Alto, CA, 26. March 2013 - 27. March 2013)
In: Proc. 9th Workshop on Silicon Errors in Logic - System Effects, München: 2013
URL: http://www.selse.org
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Kern A.:
Ethernet and IP for Automotive E/E-Architectures - Technology, Analysis, Migration Concepts and Infrastructure (Dissertation, 2013)
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Membarth R.:
Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging (Dissertation, 2013)
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Mostaghim S., Teich J.:
Strategies for finding good local guides in multi-objective particle swarm optimization (MOPSO)
2003 IEEE Swarm Intelligence Symposium, SIS 2003
DOI: 10.1109/SIS.2003.1202243
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Mühlenthaler M., Wanka R.:
A Decomposition of the Max-min Fair Curriculum-based Course Timetabling Problem: The Impact of Solving Subproblems to Optimality
6th Multidisciplinary International Scheduling Conference: Theory and Applications (MISTA) (Gent)
In: Proc. 6th Multidisciplinary International Scheduling Conference: Theory and Applications 2013
URL: http://www12.informatik.uni-erlangen.de/people/rwanka/publications/MW13.php
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Pourmohseni B., Eshghi M.:
Reliable Energy-Efficient Dynamic TDMA MAC Protocol for Wireless Body Area Networks
In: International journal of application or innovation in engineering & management (2013)
ISSN: 2319-4847
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Reimann F., Glaß M., Teich J.:
Migration Strategies for Ethernet-based E/E Architectures
Embedded World Conference (Nuremberg, 26. February 2013 - 28. February 2013)
In: Proc. Embedded World Conference, Nuremberg, Germany: 2013
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Reimann F., Glaß M., Teich J., Abelein U.:
Szenarienbasierte Integration von Diagnosefunktionalität in E/E Architekturen
Automotive meets Electronics (AmE) (Dortmund, 19. February 2013 - 20. February 2013)
In: Proc. Automotive meets Electronics, GMM Fachbericht 75, Berlin, Germany: 2013
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Reimann F., Graf S., Streit F., Glaß M., Teich J.:
Timing Analysis of Ethernet AVB-based Automotive E/E Architectures
IEEE International Conference on Emerging Technology & Factory Automation (ETFA) (Cagliari, 10. September 2013 - 13. September 2013)
In: Proc. IEEE International Conference on Emerging Technology & Factory Automation, Red Hook, NY, USA: 2013
DOI: 10.1109/ETFA.2013.6648024
URL: http://www.etfa2013.org
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Roloff S., Weichslgartner A., Heißwolf J., Hannig F., Teich J.:
NoC Simulation in Heterogeneous Architectures for PGAS Programming Model
16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES) (St. Goar, 19. June 2013 - 21. June 2013)
In: Proc. 16th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2013
DOI: 10.1145/2463596.2463606
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Schmid M., Blocherer M., Hannig F., Teich J.:
Real-Time Range Image Preprocessing on FPGAs
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, 9. December 2013 - 11. December 2013)
In: Proc. International Conference on Reconfigurable Computing and FPGAs 2013
DOI: 10.1109/ReConFig.2013.6732325
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Schmitt M., Wanka R.:
Exploiting Independent Subformulas: A Faster Approximation Scheme for #k-SAT
In: Information Processing Letters 113 (2013), p. 337-344
ISSN: 0020-0190
DOI: 10.1016/j.ipl.2013.02.013
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Schmitt M., Wanka R.:
Particles Prefer Walking Along the Axes: Experimental Insights into the Behavior of a Particle Swarm
Genetic and Evolutionary Computation Conference (GECCO) (Amsterdam, 6. July 2013 - 10. July 2013)
In: Companion of Proc. 15th Genetic and Evolutionary Computation Conference 2013
DOI: 10.1145/2464576.2464583
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Schmitt M., Wanka R.:
Particle Swarm Optimization Almost Surely Finds Local Optima
Genetic and Evolutionary Computation Conference (GECCO) (Amsterdam)
In: Proc. 15th Genetic and Evolutionary Computation Conference 2013
DOI: 10.1145/2463372.2463563
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Sousa É., Tanase AP., Hannig F., Teich J.:
Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
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Sousa É., Tanase AP., Hannig F., Teich J.:
A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
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Sousa É., Tanase AP., Lari V., Hannig F., Teich J., Paul J., Stechele W., Kröhnert M., Asfour T.:
Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
In: Proc. 25th Workshop on Parallel Systems and Algorithms, Berlin, Germany: 2013
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Tanase AP., Lari V., Hannig F., Teich J.:
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing
International Conference on Parallel Computing (ParCo) (Munich, 10. September 2013 - 13. September 2013)
In: Proc. International Conference on Parallel Computing 2013
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Teich J., Schröder-Preikschat W., Herkersdorf A.:
Invasive Computing - Common Terms and Granularity of Invasion
Cornell: Cornell University Library, 2013
(Dagstuhl Preprint Serie)
URL: http://arxiv.org/pdf/1304.6067v1.pdf
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Teich J., Tanase AP., Hannig F.:
Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567543
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Wildermann S., Teich J.:
Decomposing Run-time Resource Management in Heterogeneous Reconfigurable Systems
Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) (Porto)
In: Proc. Workshop on Self-Awareness in Reconfigurable Computing Systems 2013
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Wildermann S., Ziermann T., Teich J.:
Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems
Design, Automation and Test in Europe (DATE) (Grenoble, 18. March 2013 - 22. March 2013)
In: Proc. Design, Automation and Test in Europe, New York, NY, USA: 2013
DOI: 10.7873/DATE.2013.305
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Xu Y., Wang B., Hasholzner R., Rosales R., Teich J.:
On robust task-accurate performance estimation
50th Annual Design Automation Conference, DAC 2013 (Austin, TX, 2. June 2013 - 6. June 2013)
In: Proceedings of the 50th Design Automation Conference (DAC 2013) 2013
DOI: 10.1145/2463209.2488945
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Xu Y., Wang B., Rosales R., Hasholzner R., Teich J.:
On confident task-accurate performance estimation
26th International Conference on Architecture of Computing Systems, ARCS 2013 (Prague)
In: Proceedings of the International Conference on Architecture of Computing Systems (ARCS) 2013
DOI: 10.1007/978-3-642-36424-2_3
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Zaib A., Heisswolf J., Weichslgartner A., Wild T., Teich J., Becker J., Herkersdorf A.:
AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections
16th Euromicro Conference on Digital System Design (Cantabria, 4. September 2013 - 6. September 2013)
In: Proc. 16th Euromicro Conference on Digital System Design 2013
DOI: 10.1109/DSD.2013.87
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Zebelein C., Haubelt C., Falk J., Schwarzer T., Teich J.:
Representing mapping and scheduling decisions within dataflow graphs
2013 16th Forum on Specification and Design Languages, FDL 2013 (Paris, 24. September 2013 - 26. September 2013)
In: Proceedings of Forum on Specification & Design Languages (FDL 2013) 2013
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84891286674&origin=inward
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Zebelein C., Haubelt C., Falk J., Teich J.:
Model-Based Representation of Schedules for Dataflow Graphs
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2013) (Rostock, 12. March 2013 - 14. March 2013)
In: Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2013) 2013
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Zhang L., Glaß M., Ballmann N., Teich J.:
Bridging Algorithm and ESL Design: Matlab/Simulink Model Transformation and Validation
Forum on Specification & Design Languages (FDL) (Paris, 24. September 2013 - 26. September 2013)
In: Proc. Forum on Specification & Design Languages, New York, NY, USA: 2013
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Ziermann T., Salcic Z., Teich J.:
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN)
26th International Conference on Architecture of Computing Systems (ARCS) (Prague, 19. February 2013 - 22. February 2013)
In: Proc. 26th International Conference on Architecture of Computing Systems, New York, NY, USA: 2013
DOI: 10.1007/978-3-642-36424-2_14
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Ziermann T., Wildermann S., Teich J.:
Self-organizing Core Allocation
Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS) (Erlangen, 11. April 2013 - 12. April 2013)
In: Proc. Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware 2013
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Aliee H., Zarandi HR.:
A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays
In: IEEE Transactions on Reliability 62 (2012), p. 13-22
ISSN: 0018-9529
DOI: 10.1109/TR.2012.2221012
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Berndt R., Bazan P., Hielscher KS., German R., Lukasiewycz M.:
Multi-Valued Decision Diagrams for the Verification of Consistency in Automotive Product Data
QSIC 2012 (Xi'an, 27. August 2012 - 29. August 2012)
In: Proceedings of 12th International Conference on Quality Software (IEEE) 2012
DOI: 10.1109/QSIC.2012.43
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6319247
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Dennl C., Ziener D., Teich J.:
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library
IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (Toronto, 29. April 2012 - 1. May 2012)
In: Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), New York, NY, USA: 2012
DOI: 10.1109/FCCM.2012.18
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Eberl M., Glaß M., Teich J., Abelein U.:
Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks
The 49th Annual Design Automation Conference 2012 (DAC) (San Francisco, CA, 3. June 2012 - 7. June 2012)
In: Proc. of The 49th Annual Design Automation Conference 2012 (DAC), New York, NY, USA: 2012
DOI: 10.1145/2228360.2228400
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Farbeh H., Fazeli M., Khosravi F., Miremadi SG.:
Memory mapped SPM: Protecting instruction scratchpad memory in embedded systems against soft errors
9th European Dependable Computing Conference, EDCC 2012 (Sibiu, 8. May 2012 - 11. May 2012)
In: Proceedings of the 9th European Dependable Computing Conference (EDCC 2012) 2012
DOI: 10.1109/EDCC.2012.13
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Fekete SP., Kamphans T., Schweer N., Tessars C., Van Der Veen JC., Angermeier J., Koch D., Teich J.:
Dynamic Defragmentation of Reconfigurable Devices
In: ACM Transactions on Reconfigurable Technology and Systems 5 (2012), p. 1-20
ISSN: 1936-7406
DOI: 10.1145/2209285.2209287
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Gerndt M., Hannig F., Herkersdorf A., Hollmann A., Meyer M., Roloff S., Weidendorfer J., Wild T., Zaib A.:
An Integrated Simulation Framework for Invasive Computing
Forum on Specification & Design Languages (FDL) (Vienna, 18. September 2012 - 20. September 2012)
In: Proc. of the Forum on Specification & Design Languages (FDL), New York, NY, USA: 2012
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Gladigau J., Haubelt C., Teich J.:
Model-Based Virtual Prototype Acceleration
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31 (2012), p. 1572-1585
ISSN: 0278-0070
DOI: 10.1109/TCAD.2012.2205148
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Glaß M., Teich J., Zhang L.:
A Co-simulation Approach for System-Level Analysis of Embedded Control Systems
2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (Samos, 16. July 2012 - 19. July 2012)
In: Proc. of the 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), New York, NY, USA: 2012
DOI: 10.1109/SAMOS.2012.6404200
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Glaß M., Yu H., Reimann F., Teich J.:
Cross-Level Compositional Reliability Analysis for Embedded Systems
31st International Conference on Computer Safety, Reliability, and Security (SAFECOMP) (Magdeburg, 25. September 2012 - 28. September 2012)
In: Proc. of the 31st International Conference on Computer Safety, Reliability, and Security (SAFECOMP), Berlin; Heidelberg: 2012
DOI: 10.1007/978-3-642-33678-2_10
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Graf S., Glaß M., Teich J.:
Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (Kaiserslautern, 5. March 2012 - 7. March 2012)
In: Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Hamburg, Germany: 2012
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Graf S., Russ T., Glaß M., Teich J.:
Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures
Automotive meets Electronics (AmE), GMM Fachbericht 72 (Dortmund)
In: Proc. of Automotive meets Electronics (AmE), GMM Fachbericht 72, Berlin, Germany: 2012
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Heisswolf J., Zaib A., Weichslgartner A., König R., Wild T., Teich J., Herkersdorf A., Becker J.:
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS
26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW) (Shanghai, 21. May 2012 - 25. May 2012)
In: Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), New York, NY, USA: 2012
DOI: 10.1109/IPDPSW.2012.25
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Henkel J., Herkersdorf A., Bauer L., Wild T., Hübner M., Pujari RK., Grudnitsky A., Heisswolf J., Zaib A., Vogel B., Lari V., Kobbe S.:
Invasive Manycore Architectures
17th Asia and South Pacific Design Automation Conference (ASP-DAC) (Sydney, 30. January 2012 - 2. February 2012)
In: Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), New York, NY, USA: 2012
DOI: 10.1109/ASPDAC.2012.6164944
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Kiesel R., Streubühr M., Haubelt C., Terzis A., Teich J.:
Virtual prototyping for efficient multi-core ECU development of driver assistance systems
2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012 (Samos, 16. July 2012 - 19. July 2012)
In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XII) 2012
DOI: 10.1109/SAMOS.2012.6404155
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Koch D., Torresen J., Beckhoff C., Ziener D., Dennl C., Breuer V., Teich J., Feilen M., Stechele W.:
Partial Reconfiguration on FPGAs in Practice - Tools and Applications
25th International Conference on Architecture of Computing Systems (ARCS) (Munich, 28. February 2012 - 2. March 2012)
In: Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), New York, NY, USA: 2012
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Lari V., Muddasani S., Boppu S., Hannig F., Schmid M., Teich J.:
Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays
In: ACM Transactions on Design Automation of Electronic Systems 18 (2012), p. 1-25
ISSN: 1084-4309
DOI: 10.1145/2390191.2390193
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Lari V., Muddasani S., Boppu S., Hannig F., Teich J.:
Design of low power on-chip processor arrays
2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012 (Delft, 9. July 2012 - 11. July 2012)
In: Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2012
DOI: 10.1109/ASAP.2012.10
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Lukasiewycz M., Glaß M., Teich J., Milbredt P.:
FlexRay Static Segment Scheduling
In: Advances in Real-Time Systems, Berlin; Heidelberg: Springer-Verlag, 2012, p. 323-339
ISBN: 978-3-642-24348-6
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Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging
11th International Symposium on Parallel and Distributed Computing (ISPDC) (Munich, 25. June 2012 - 29. June 2012)
In: Proc. of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), New York, NY, USA: 2012
DOI: 10.1109/ISPDC.2012.36
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Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
Generating Device-specific GPU Code for Local Operators in Medical Imaging
26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) (Shanghai, 21. May 2012 - 25. May 2012)
In: Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), New York, NY, USA: 2012
DOI: 10.1109/IPDPS.2012.59
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Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
Mastering Software Variant Explosion for GPU Accelerators
In: Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), Berlin; Heidelberg: Springer, 2012, p. 123-132 (Lecture Notes on Computer Science (LNCS))
DOI: 10.1007/978-3-642-36949-0_15
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Membarth R., Hannig F., Teich J., Köstler H.:
Towards Domain-specific Computing for Stencil Codes in HPC
2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (Salt Lake City, UT, 10. November 2012 - 16. November 2012)
In: Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) 2012
DOI: 10.1109/SC.Companion.2012.136
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Membarth R., Lupp JH., Hannig F., Teich J., Körner M., Eckert W.:
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging
25th International Conference on Architecture of Computing Systems (ARCS) (Munich, 28. February 2012 - 2. March 2012)
In: Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), New York, NY, USA: 2012
DOI: 10.1007/978-3-642-28293-5_13
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Milbredt P., Glaß M., Lukasiewycz M., Steininger A., Teich J.:
Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach
Design, Automation and Test in Europe (DATE) (Dresden, Germany, 12. March 2012 - 16. March 2012)
In: Proc. of Design, Automation and Test in Europe (DATE), New York, NY, USA: 2012
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Muddasani S., Boppu S., Hannig F., Kuzmin B., Lari V., Teich J.:
A Prototype of an Invasive Tightly-Coupled Processor Array
2012 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Karlsruhe, 23. October 2012 - 25. October 2012)
In: Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), New York, NY, USA: 2012
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Mühlenthaler M., Wanka R.:
Fairness in Academic Timetabling
9th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT) (Son, 28. August 2012 - 31. August 2012)
In: Proc. 9th Int. Conf. on the Practice and Theory of Automated Timetabling (PATAT) 2012
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Riess C., Strehl V., Wanka R.:
The Spectral Relation between the Cube-Connected Cycles and the Shuffle-Exchange Network
10th Workshop on Parallel Systems and Algorithms (PASA) of the 25th Int. Conf. on Architecture of Computing Systems (ARCS) (München)
In: GI (ed.): Proc. 10th Workshop on Parallel Systems and Algorithms (PASA) of the 25th Int. Conf. on Architecture of Computing Systems (ARCS) 2012
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Roloff S., Hannig F., Teich J.:
Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs
17th Asia and South Pacific Design Automation Conference (ASP-DAC) (Sydney, 30. January 2012 - 2. February 2012)
In: Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), New York, NY, USA: 2012
DOI: 10.1109/ASPDAC.2012.6164943
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Roloff S., Hannig F., Teich J.:
Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation
15th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Schloss Rheinfels, St. Goar, 15. May 2012 - 16. May 2012)
In: Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), New York, NY, USA: 2012
DOI: 10.1145/2236576.2236582
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Roloff S., Hannig F., Teich J.:
Simulation of Resource-Aware Applications on Heterogeneous Architectures
8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. July 2012 - 14. July 2012)
In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
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Rosales R., Klie T., Glock S., Xu Y., Wang B., Hasholzner R., Teich J., Weigel R.:
Eine Aktor-Orientierte Methodik zur Power-Modellierung auf Systemebene
In: Design & Elektronik (2012), p. 1-9
ISSN: 0933-8667
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Schmid M., Hannig F., Teich J.:
Power Management Strategies for Serial RapidIO Endpoints in FPGAs
IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (Toronto, 29. April 2012 - 1. May 2012)
In: Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), New York, NY, USA: 2012
DOI: 10.1109/FCCM.2012.26
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Tanase AP., Hannig F., Teich J.:
Symbolic loop parallelization of static control programs
8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. July 2012 - 14. July 2012)
In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
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Teich J.:
Hardware/Software Co-Design: Past, Present, and Predicting the Future
In: Proceedings of the IEEE 100 (2012), p. 1411-1430
ISSN: 0018-9219
DOI: 10.1109/JPROC.2011.2182009
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Teich J., Weichslgartner A., Oechslein B., Schröder-Preikschat W.:
Invasive Computing - Concepts and Overheads
Forum on Specification & Design Languages (FDL) (Vienna, 18. September 2012 - 20. September 2012)
In: Proc. of the Forum on Specification & Design Languages (FDL), New York, NY, USA: 2012
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Wildermann S.:
Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing (Dissertation, 2012)
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Wildermann S., Angermeier J., Sibirko E., Teich J.:
Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures
In: International Journal of Reconfigurable Computing 2012 (2012), p. 1-12
ISSN: 1687-7195
DOI: 10.1155/2012/608312
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Wildermann S., Reimann F., Ziener D., Teich J.:
Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems
In: Design Automation For Embedded Systems (2012), p. 1-33
ISSN: 0929-5585
DOI: 10.1007/s10617-012-9102-1
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Wildermann S., Reimann F., Ziener D., Teich J.:
System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems
Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) (Oslo, 1. September 2012 - 1. September 2012)
In: Proc. of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) 2012
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Xu Y., Rosales R., Wang B., Streubühr M., Hasholzner R., Haubelt C., Teich J.:
A very fast and quasi-accurate power-state-based system-level power modeling methodology
25th International Conference on Architecture of Computing Systems, ARCS 2012 (Munich)
In: Proceedings of the International Conference on Architecture of Computing Systems (ARCS) 2012
DOI: 10.1007/978-3-642-28293-5_4
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Zebelein C., Falk J., Haubelt C., Teich J.:
A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs
2nd Electronic System Level Synthesis Conference, ESLsyn 2012 (San Francisco, CA, 2. June 2012 - 3. June 2012)
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84866155902&origin=inward
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Zebelein C., Falk J., Haubelt C., Teich J.:
Exploiting Model-Knowledge in High-Level Synthesis
Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’12) (Kaiserslautern, 5. March 2012 - 7. March 2012)
In: Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’12) 2012
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Zhang L., Glaß M., Streubühr M., Teich J., von Schwerin A., Liu K.:
Actor-oriented Modeling and Simulation of Cut-through Communication in Network Controllers
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (Kaiserslautern, 5. March 2012 - 7. March 2012)
In: Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Hamburg, Germany: 2012
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Zhang L., Streubühr M., Glaß M., Teich J., von Schwerin A., Liu K.:
System-Level Modeling and Simulation of Networked PROFINET IO Controllers
Embedded World Conference (Nuremberg, 28. February 2012 - 1. March 2013)
In: Proc. of the Embedded World Conference, Kissingen, Germany: 2012
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Ziermann T., Butiu A., Teich J., Ziener D.:
FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN)
2012 International Conference on Reconfigurable Computing (ReConFig) (Cancun, 5. December 2012 - 7. December 2012)
In: Proc. of the 2012 International Conference on Reconfigurable Computing (ReConFig), New York, NY, USA: 2012
DOI: 10.1109/ReConFig.2012.6416750
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Ziermann T., Salcic Z., Teich J.:
Improving Performance of Controller Area Network (CAN) by Adaptive Message Scheduling
In: Self-Organization in Embedded Real-Time Systems, Berlin; Heidelberg: Springer-Verlag, 2012, p. 95-120
ISBN: 978-1-4614-1968-6
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Ziermann T., Wildermann S., Mühleis N., Teich J.:
Distributed self-organizing bandwidth allocation for priority-based bus communication
In: Concurrency and Computation-Practice & Experience 24 (2012), p. 1903-1917
ISSN: 1532-0626
DOI: 10.1002/cpe.1759
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Aliee H., Zarandi HR.:
A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors
30th International Conference on Computer Safety, Reliability and Security, SAFECOMP 2011 (Naples)
In: Proceedings of the 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP'11) 2011
DOI: 10.1007/978-3-642-24270-0_24
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Aliee H., Zarandi HR.:
An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems
13th European Workshop on Dependable Computing, EWDC 2011 (Pisa)
In: roceedings of the 13th European Workshop on Dependable Computing (EWDC '11) 2011
DOI: 10.1145/1978582.1978594
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Aliee H., Zarandi HR.:
Fault tree analysis using stochastic logic: A reliable and high speed computing
Annual Reliability and Maintainability Symposium, RAMS 2011 (Lake Buena Vista, FL)
DOI: 10.1109/RAMS.2011.5754466
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Aliee H., Zarandi HR., Tajary A.:
CPU-aware, process-level redundancy to tolerate faults in multi-core
2011 International Conference on High Performance Computing and Simulation, HPCS 2011 (Istanbul)
DOI: 10.1109/HPCSim.2011.5999844
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Angermeier J., Sibirko E., Wanka R., Teich J.:
Bitonic Sorting on Dynamically Reconfigurable Architectures
IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) (Anchorage, AL, 16. May 2011 - 20. May 2011)
In: Proc. IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), New York, NY, USA: 2011
DOI: 10.1109/IPDPS.2011.164
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Angermeier J., Ziener D., Glaß M., Teich J.:
Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints
International Conference on Field-Programmable Technology (FPT'11) (New Delhi, 12. December 2011 - 14. December 2011)
In: Proceedings of the International Conference on Field-Programmable Technology, New York, NY, USA: 2011
DOI: 10.1109/FPT.2011.6133247
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Angermeier J., Ziener D., Glaß M., Teich J.:
Stress-Aware Module Placement on Reconfigurable Devices
International Conference on Field Programmable Logic and Applications (FPL'11) (Chania, Crete, 5. September 2011 - 7. September 2011)
In: Proceedings of the International Conference on Field-Programmable Logic and Applications, New York, NY, USA: 2011
DOI: 10.1109/FPL.2011.56
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Boppu S., Hannig F., Teich J., Pérez-Andrade R.:
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays
2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig'11) (Cancun, 30. November 2011 - 2. December 2011)
In: Proc. of ReConFig, New York, NY, USA: 2011
DOI: 10.1109/ReConFig.2011.91
URL: http://www.computer.org/portal/web/csdl/doi/10.1109/ReConFig.2011.91
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Cavallaro JR., Ercegovac MD., Hannig F., Ienne P., Swartzlander Jr. EE., Tenca AF. (ed.):
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
New York, NY, USA: 2011
ISBN: 978-1-4577-1292-0
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Dutta H.:
Synthesis and Exploration of Loop Accelerators for Systems-on-a-Chip (Dissertation, 2011)
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Falk J., Zebelein C., Haubelt C., Teich J.:
A rule-based static dataflow clustering algorithm for efficient embedded software synthesis
14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011 (Grenoble, 14. March 2011 - 18. March 2011)
In: Proceedings of Design, Automation and Test in Europe (DATE'11) 2011
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=79957549287&origin=inward
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Gladigau J., Gerstlauer A., Haubelt C., Streubühr M., Teich J.:
Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs
In: LNCS Transactions on High-Performance Embedded Architectures and Compilers 5 (2011), p. 1-22
ISSN: 1864-306X
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Glaß M.:
Dependability-Aware System-Level Design for Embedded Systems (Dissertation, 2011)
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Graf S., Streubühr M., Glaß M., Teich J.:
Analyzing Automotive Networks using Virtual Prototypes
Automotive meets Electronics (AmE), GMM Fachbericht 69 (Dortmund, Germany)
In: Proceedings of the Automotive meets Electronics (AmE2011), GMM Fachbericht 69, Berlin: 2011
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Hannig F., Roloff S., Snelting G., Teich J., Zwinkau A.:
Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10
14th International Workshop on Software and Compilers for Embedded Systems (St. Goar, 27. June 2011 - 28. June 2011)
In: Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2011
DOI: 10.1145/1988932.1988941
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Helwig S., Neumann F., Wanka R.:
Velocity Adaptation in Particle Swarm Optimization
In: Handbook of Swarm Intelligence, Heidelberg: Springer, 2011, p. 155-173 (Adaptation, Learning, and Optimization (ALO), Vol.8)
DOI: 10.1007/978-3-642-17390-5_7
URL: https://www12.cs.fau.de/people/rwanka/publications/HNW11.php
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Henkel J., Bauer L., Becker J., Bringmann O., Brinkschulte U., Chakraborty S., Engel M., Ernst R., Härtig H., Hedrich L., Herkersdorf A., Kapitza R., Lohmann D., Marwedel P., Platzner M., Rosenstiel W., Schlichtmann U., Spinczyk O., Tahoori M., Teich J., Wehn N., Wunderlich HJ.:
Design and Architectures for Dependable Embedded Systems
9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '11) (Taipei, 9. October 2011 - 14. October 2011)
In: Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '11), New York, NY, USA: 2011
DOI: 10.1145/2039370.2039384
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Hoffmann M., Mühlenthaler M., Helwig S., Wanka R.:
Discrete Particle Swarm Optimization for TSP: Theoretical Results and Experimental Evaluations
International Conference on Adaptive and Intelligent Systems (ICAIS) (Klagenfurt)
In: Bouchachia A. (ed.): Proc. International Conference on Adaptive and Intelligent Systems (ICAIS), Berlin, Heidelberg: 2011
DOI: 10.1007/978-3-642-23857-4_40
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Keinert J., Teich J.:
Design of Image Processing Embedded Systems Using Multidimensional Data Flow
Heidelberg: Springer-Verlag, 2011
(Embedded Systems)
ISBN: 978-1-4419-7181-4
URL: http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-7181-4
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Kern A., Reinhard D., Streichert T., Teich J.:
Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa
24th International Conference on Architecture of Computing Systems (ARCS'11) (Lake Como, 24. February 2011 - 25. February 2011)
In: Proceedings of the 24th International Conference on Architecture of Computing Systems, Berlin; Heidelberg: 2011
DOI: 10.1007/978-3-642-19137-4_22
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Kern A., Streichert T., Teich J.:
An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP)
Design, Automation and Test in Europe (DATE'11) (Grenoble, 14. March 2011 - 18. March 2011)
In: Proc. of DATE, New York, NY, USA: 2011
URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763027
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Kern A., Zhang H., Streichert T., Teich J.:
Testing Switched Ethernet Networks in Automotive Embedded Systems
6th IEEE International Symposium on Industrial Embedded Systems (SIES'11) (Västeras, 15. June 2011 - 17. June 2011)
In: Proceedings of the 6th IEEE International Symposium on Industrial Embedded Systems (SIES'11), New York, NY, USA: 2011
DOI: 10.1109/SIES.2011.5953657
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Kern A., Zinner H., Streichert T., Nöbauer J., Teich J.:
Accuracy of Ethernet AVB Time Synchronization Under Varying Temperature Conditions for Automotive Networks
ACM/EDAC/IEEE Design Automation Conference (DAC'11) (San Diego, California, 5. June 2011 - 9. June 2011)
In: Proceedings of the 2011 ACM/EDAC/IEEE Design Automation Conference (DAC'11), New York, NY, USA: 2011
DOI: 10.1145/2024724.2024862
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Khosravi F., Farbeh H., Fazeli M., Miremadi SG.:
Low cost concurrent error detection for on-chip memory based embedded processors
2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011 (Melbourne, VIC)
In: Proceedings of the 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2011) 2011
DOI: 10.1109/EUC.2011.47
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Kiesel R., Streubühr M., Haubelt C., Löhlein O., Teich J.:
Calibration and validation of software performance models for pedestrian detection systems
2011 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011 (Samos)
In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI) 2011
DOI: 10.1109/SAMOS.2011.6045460
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Kissler D.:
Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing (Dissertation, 2011)
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Kissler D., Gran D., Salcic Z., Hannig F., Teich J.:
Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays
In: IEEE Embedded Systems Letters 3 (2011), p. 58-61
ISSN: 1943-0663
DOI: 10.1109/LES.2011.2124438
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Kissler D., Hannig F., Teich J.:
Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays
In: Journal of Low Power Electronics 7 (2011), p. 29-40
ISSN: 1546-1998
DOI: 10.1166/jolpe.2011.1114
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Kouveli G., Hannig F., Lupp JH., Teich J.:
Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor
3rd Many-core Applications Research Community (MARC) Symposium (Ettlingen, 5. July 2011 - 6. July 2011)
In: Proceedings of the 3rd MARC Symposium, Karlsruhe, Germany: 2011
DOI: 10.5445/KSP/1000023937
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Kutzer P., Gladigau J., Haubelt C., Teich J.:
Automatic generation of system-level virtual prototypes from streaming application models
2011 22nd IEEE International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP-2011 (Karlsruhe)
In: Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping 2011
DOI: 10.1109/RSP.2011.5929986
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Kutzer P., Streubühr M., Haubelt C., Teich J., von Schwerin A.:
Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC
Embedded World Conference (Nuermberg, 1. March 2011 - 3. March 2011)
In: Proceedings of the Embedded World Conference 2011
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Lari V., Hannig F., Teich J.:
Distributed Resource Reservation in Massively Parallel Processor Arrays
25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS'11) (Anchorage, AK, 16. May 2011 - 20. May 2011)
In: Proc. of the 25th IEEE International Symposium on Parallel and Distributed Processing, New York, NY, USA: 2011
DOI: 10.1109/IPDPS.2011.157
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Lari V., Narovlyanskyy A., Hannig F., Teich J.:
Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'11) (Santa Monica, CA, 11. September 2011 - 14. September 2011)
In: Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, New York, NY, USA: 2011
DOI: 10.1109/ASAP.2011.6043240
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Lukasiewycz M., Glaß M., Reimann F., Teich J.:
Opt4J - A Modular Framework for Meta-heuristic Optimization
13th Annual Genetic and Evolutionary Computation Conference (GECCO'11) (Dublin, 12. July 2011 - 16. July 2011)
In: Proc. of the 13th Annual Genetic and Evolutionary Computation Conference, New York, NY, USA: 2011
DOI: 10.1145/2001576.2001808
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Majer M.:
The Erlangen Slot Machine - An FPGA-Based Partially Reconfigurable Computer (Dissertation, 2011)
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Marwedel P., Teich J., Kouveli G., Bacivarov I., Thiele L., Ha S., Lee C., Xu Q., Huang L.:
Mapping of Applications to MPSoCs
9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11) (Taipei, 9. October 2011 - 14. October 2011)
In: Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, part of ESWeek'11, New York, NY, USA: 2011
DOI: 10.1145/2039370.2039390
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Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration
9th IEEE Symposium on Application Specific Processors (SASP) (San Diego, CA, USA, 5. June 2011 - 6. June 2011)
In: Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP) 2011
DOI: 10.1109/SASP.2011.5941083
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Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration
24th International Conference on Architecture of Computing Systems (ARCS) (Lake Como, 24. February 2011 - 25. February 2011)
In: Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), Heidelberg: 2011
DOI: 10.1007/978-3-642-19137-4_6
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Membarth R., Hannig F., Teich J., Litz G., Hornegger H.:
Detector Defect Correction of Medical Images on Graphics Processors
SPIE: Medical Imaging : Image Processing (Lake Buena Vista, Orlando, FL, 14. February 2011 - 16. February 2011)
In: Proceedings of the SPIE: Medical Imaging 2011: Image Processing 2011
DOI: 10.1117/12.877656
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Membarth R., Lokhmotov A., Teich J.:
Generating GPU Code from a High-level Representation for Image Processing Kernels
5th Workshop on Highly Parallel Processing on a Chip (HPPC) (Bordeaux)
In: Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC) 2011
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Mühleis N., Glaß M., Zhang L., Teich J.:
A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems
2nd International Conference on Cyber Physical Systems (ICCPS 2011)
In: ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems (ICCPS 2011) 2011
DOI: 10.1145/2000367.2000372
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Omeltschuk L., Helwig S., Mühlenthaler M., Wanka R.:
Heterogeneous Constraint Handling for Particle Swarm Optimization
IEEE Swarm Intelligence Symposium (SIS) (Paris, 11. April 2011 - 15. April 2011)
In: Proc. IEEE Swarm Intelligence Symposium (SIS), New York, NY, USA: 2011
DOI: 10.1109/SIS.2011.5952578
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Reimann F., Lukasiewycz M., Glaß M., Haubelt C., Teich J.:
Symbolic system synthesis in the presence of stringent real-time constraints
2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (San Diego, CA, 5. June 2011 - 10. June 2011)
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=80052678758&origin=inward
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Streubühr M., Rosales R., Hasholzner R., Haubelt C., Teich J.:
ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC
Forum on specification and Design Languages 2011 (Oldenbúrg, 13. September 2011 - 15. September 2011)
In: Forum on specification and Design Languages 2011 2011
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Teich J., Henkel J., Herkersdorf A., Schmitt-Landsiedel D., Schröder-Preikschat W., Snelting G.:
Invasive Computing: An Overview
In: M. Hübner and J. Becker (ed.): Multiprocessor System-on-Chip - Hardware Design and Tool Integration, New York: Springer, 2011, p. 241-268
ISBN: 978-1-4419-6459-5
DOI: 10.1007/978-1-4419-6460-1_11
URL: http://invasic.informatik.uni-erlangen.de/publications/invasic-overview.pdf
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Teich J., Ziener D.:
Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques (Keynote)
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11) (Las Vegas)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2011
URL: http://ersaconf.org/ersa11/program/teich.php
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Wanka R.:
Parallel Sorting - The Need for Speed
In: Algorithms Unplugged, Heidelberg: Springer, 2011, p. 27-37
ISBN: 978-3-642-15327-3
DOI: 10.1007/978-3-642-15328-0_4
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Wasza J., Bauer S., Haase S., Schmid M., Reichert S., Hornegger J.:
RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing
VMV 2011: Vision, Modeling & Visualization (Berlin, 4. October 2011)
In: Eisert Peter, Hornegger Joachim, Polthier Konrad (ed.): VMV 2011: Vision, Modeling & Visualization 2011
DOI: 10.2312/PE/VMV/VMV11/057-064
URL: http://www5.informatik.uni-erlangen.de/Forschung/Publikationen/2011/Wasza11-RTR.pdf
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Weichslgartner A., Wildermann S., Teich J.:
Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures
Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11) (Pittsburgh, 1. May 2011 - 4. May 2011)
In: Proc. Fifth ACM/IEEE International Symposium on Networks-on-Chip, New York, NY, USA: 2011
DOI: 10.1145/1999946.1999979
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Wildermann S., Reimann F., Teich J., Salcic Z.:
Operational Mode Exploration for Reconfigurable Systems with Multiple Applications
International Conference on Field-Programmable Technology (FPT'11) (New Delhi, 12. December 2011 - 14. December 2011)
In: Proceedings of the International Conference on Field-Programmable Technology, New York, NY, USA: 2011
DOI: 10.1109/FPT.2011.6132693
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Wildermann S., Reimann F., Ziener D., Teich J.:
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems
9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11) (Taipei, 9. October 2011 - 14. October 2011)
In: Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, part of ESWeek'11, New York, NY, USA: 2011
DOI: 10.1145/2039370.2039393
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Wildermann S., Ziener D., Teich J.:
Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs
International Conference on Field Programmable Logic and Applications (FPL'11) (Chania, Crete, 5. September 2011 - 7. September 2011)
In: Proc. of the International Conference on Field Programmable Logic and Applications, New York, NY, USA: 2011
DOI: 10.1109/FPL.2011.85
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Ziener D., Wildermann S., Oetken A., Weichslgartner A., Teich J.:
A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC
Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011 (Chania, Crete, 4. September 2011 - 4. September 2011)
In: Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at FPL 2011 2011
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Ziermann T., Salcic Z., Teich J.:
DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems
Design, Automation and Test in Europe (DATE'11) (Grenoble, 14. March 2011 - 18. March 2011)
In: Proc. of DATE, New York, NY, USA: 2011
URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763272
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Ziermann T., Salcic Z., Teich J.:
Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems
8th International Conference on Autonomic and Trusted Computing (ATC'11) (Banff, 2. September 2011 - 4. September 2011)
In: Proc. of the 8th International Conference on Autonomic and Trusted Computing, Heidelberg: 2011
DOI: 10.1007/978-3-642-23496-5_10
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Ziermann T., Schmidt B., Mühlenthaler M., Ziener D., Angermeier J., Teich J.:
An FPGA Implementation of a Threat-based Strategy for Connect6
International Conference on Field-Programmable Technology (FPT'11) (New Delhi, 12. December 2011 - 14. December 2011)
In: Proceedings of the International Conference on Field-Programmable Technology, New York, NY, USA: 2011
DOI: 10.1109/FPT.2011.6133250
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Ziermann T., Wildermann S., Teich J.:
OrganicBus: Organic Self-organising Bus-Based Communication Systems
In: Organic Computing - A Paradigm Shift for Complex Systems, Basel: Birkhäuser Verlag, 2011, p. 489-501
ISBN: 978-3-0348-0130-0
DOI: 10.1007/978-3-0348-0130-0_32
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Ahmadinia A., Angermeier J., Fekete SP., Kamphans T., Koch D., Majer M., Schweer N., Teich J., Tessars C., Van Der Veen JC.:
ReCoNodes-optimization methods for module scheduling and placement on reconfigurable hardware devices
Springer Netherlands, 2010
ISBN: 9789048134847
DOI: 10.1007/978-90-481-3485-4_10
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Angermeier J., Bobda C., Majer M., Teich J.:
Erlangen slot machine: An FPGA-based dynamically reconfigurable computing platform
Springer Netherlands, 2010
ISBN: 9789048134847
DOI: 10.1007/978-90-481-3485-4_3
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Angermeier J., Teich J., Kamphans T., Fekete SP.:
Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices
17th Reconfigurable Architectures Workshop (RAW'10) (Atlanta, 19. April 2010 - 23. April 2010)
In: Proc. 17th Reconfigurable Architectures Workshop 2010
DOI: 10.1109/IPDPSW.2010.5470754
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Angermeier J., Wildermann S., Sibirko E., Teich J.:
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures
International Conference on ReConFigurable Computing and FPGAs (ReConFig'10) (Cancun, 13. December 2010 - 15. December 2010)
In: Proc. International Conference on ReConFigurable Computing and FPGAs 2010
DOI: 10.1109/ReConFig.2010.52
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Chakraborty S., Ramesh S., Teich J.:
Model-based analysis, synthesis and testing of automotive hardware/software architectures
6th Embedded Systems Week 2010, ESWEEK 2010 - 10th ACM International Conference on Compilers, Architecture and Synthesis for Embedded Systems, EMSOFT'10 (Scottsdale, AZ)
DOI: 10.1145/1879021.1879061
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Charot F., Hannig F., Teich J., Wolinski C. (ed.):
Proc. 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors
New York, NY, USA: 2010
ISBN: 978-1-4244-6967-3
DOI: 10.1109/ASAP.2010.5540766
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Dutta H., Hannig F., Schmid M., Keinert J.:
Modeling and synthesis of communication subsystems for loop accelerator pipelines
21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. July 2010 - 9. July 2010)
In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
DOI: 10.1109/ASAP.2010.5540760
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Falk J., Keinert J., Haubelt C., Teich J., Zebelein C.:
Integrated Modeling Using Finite State Machines and Dataflow Graphs
In: Bhattacharyya S., Deprettere E., Leupers R., Takala J. (ed.): Handbook of Signal Processing Systems, Boston, MA: Springer, 2010, p. 1041-1075
ISBN: 978-1-4419-6344-4
DOI: 10.1007/978-1-4419-6345-1_36
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Falk J., Zebelein C., Haubelt C., Teich J., Dorsch R.:
Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models
3. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Dresden, 22. February 2010 - 24. February 2010)
In: 3. ITG/GI/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2010
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Falk J., Zebelein C., Keinert J., Haubelt C., Teich J., Bhattacharyya SS.:
Analysis of systemc actor networks for efficient synthesis
In: ACM Transactions on Embedded Computing Systems 10 (2010), Article No.: 18
ISSN: 1539-9087
DOI: 10.1145/1880050.1880054
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Gladigau J., Gerstlauer A., Haubelt C., Streubühr M., Teich J.:
A system-level synthesis approach from formal application models to generic bus-based MPSoCs
2010 10th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulati

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