Architecture and Compiler Design
Life cycles of technical products are continuously decreasing, especially in the area of computer technology. This cascading effect becomes possible by the fact that computers themselves are used to design new powerful microprocessors for the next computer generation. Thus, the design time for new generations of microprocessors decreases rapidly.
Beyond that, in the last years, microprocessors are employed more and more in products where the presence of microprocessors is not obvious: Cellular phones, PDAs, medical technology, entertainment electronics, and in the automotive world.
Unlike typical computers like PCs and workstations, these embedded systems are specialized to a certain class of applications and highly optimized with respect to computation speed, cost, interface bandwidth, energy consumption, etc. Beside production costs, development cost and shorter time-to-market cycles have become important.
The goal in our working group “Architecture and Compiler Design (ACD)” is to shorten the design cycle when developing application specific processors. Here, the following research areas are considered: CAD tools for modelling, simulation, and the automatic generation of architectures, and compilers and mapping methodologies for these architectures.
Both micro programmable processors and dedicated hardware are investigated. The goal when designing micro programmable application specific processors is an architecture/compiler co-generation optimized for a whole class of algorithms (benchmark). Many computational applications may also be implemented directly in one dedicated massively parallel system, i.e., one highly optimized system (e.g., a co-processor) realizes exactly one application.
From these different target architectures (programmable or dedicated) a trade-off between hardware and software solutions is resulting. Here, one solution might be the consideration of reconfigurable architectures. Therefore, reconfigurable arrays and processors are part of our actual research.
Current research projects
- Dedizierte massiv parallele Systeme – Details
- HBS: Graduiertenkolleg “Heterogene Bildsysteme”, Projekt B3
- INI.FAU: Parallelisierung und Ressourcenabschätzung von Algorithmen für heterogene FAS-Architekturen
- InvasIC: Transregional Collaboriative Research Center 89 — Invasive Computing
- Basics of Invasive Computing (A01)
- Design-Time Characterisation and Analysis of Invasive Algorithmic Patterns (A04)
- Invasive Tightly-Coupled Processor Arrays (B02)
- Compilation and Code Generation for Invasive Programs (C03)
- TCPA_INT – Integration und Verbindung von eng gekoppelten Prozessorfeldern (T01)
- Central Services of the Transregional Collaborative Research Centre and Public Relations (Z01)
- Validation and Demonstrator (Z02)