Motivation

Chip design is the essential step when developing microelectronics for specific products and applications. Competence in chip design can strengthen Germany's innovation and competitiveness and increase its technological sovereignty in Europe. In order to leverage this potential, the German and European chip design ecosystem is to be expanded. To this end, the BMBF has launched the Microelectronics Design Initiative with four key areas of focus: a strong network as a central exchange platform, training and further education for talented individuals and specialists, research projects to strengthen design capabilities, and expanding research structures.

Project Goals

The aim of the project is to develop modern AI chips that are designed with a particular focus on security, trustworthiness, and energy efficiency in various application scenarios. Another goal is to implement a seamless transition from software-based AI algorithm development to efficient hardware implementation. The focus here is on the close linking of AI and hardware in the design process as well as the development of various AI accelerators and corresponding architectures. The end result should be an automated design methodology that extends from the AI software to the AI hardware.

The focus of our chair within DI-EDAI is, in particular, on the development of a co-exploration approach that optimizes both neural network models and associated AI-specific microprocessor extensions, taking into account non-functional requirements (e.g., cost, speed, accuracy, energy, security). The results, in the form of hardware blocks and EDA software, shall be published as open source and contribute to creating an ecosystem for designing sustainable and transparent AI systems.

Two-panel figure. The left panel shows a general-purpose RISC-V processor augmented with AI-specific instruction set extensions. The right panel shows a closed co-exploration loop in which AI algorithms and target hardware architectures are explored together via design space exploration; neural network models are trained and fine-tuned for the proposed extensions within an iterative cycle.
Contributions to DI-EDAI. Left: Proposed AI-specific instruction set extensions for general-purpose RISC-V processors. Right: Co-exploration loop jointly exploring AI algorithms and target architectures.

Publications

Sabih M., Karim A., Wittmann J., Hannig F., Teich J.:
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
International Conference on Field Programmable Technology (FPT) (Sydney, Australia, 10. December 2024 - 12. December 2024)
In: IEEE (ed.): Proceedings of International Conference on Field Programmable Technology (FPT) 2024
DOI: 10.1109/ICFPT64416.2024.11113397
BibTeX: Download
Tahoori M., Meyers V., Sadeghipour Roodsari M., Xu H., Becker J., Harbaum T., Frombach F., Höfer J., Sotiropoulos G., Henkel J., Demirdag Z., Khdr H., Nassar H., Schlichtmann U., Geier J., van Kempen P., Sigl G., Kögler S., Probst M., Teich J., Hannig F., Sabih M., Sesli B., Wehn N., Steiner L., Kunz W., Shelkamy Ali M.:
Special Session – Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Taipei, 28. September 2025 - 3. October 2025)
In: ACM (ed.): Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2025
DOI: 10.1145/3742873.3756928
URL: https://dl.acm.org/doi/10.1145/3742873.3756928
BibTeX: Download
Sesli B., Sabih M., Hannig F., Teich J.:
Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow
International Conference on Computer Aided Design (ICCAD) (Munich, 26. October 2025 - 30. October 2025)
In: IEEE (ed.): Proceedings of the International Conference on Computer Aided Design (ICCAD) 2025
DOI: 10.1109/ICCAD66269.2025.11240834
URL: https://ieeexplore.ieee.org/document/11240834
BibTeX: Download
Sabih M., Abdo M., Hannig F., Teich J.:
Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks using RISC-V Custom Functional Units
In: IEEE Embedded Systems Letters 17 (2025), p. 329-332
ISSN: 1943-0663
DOI: 10.1109/LES.2025.3600565
BibTeX: Download
Sotiropoulos G., Frombach F., Höfer J., Harbaum T., Becker J., Thorøe HI., Meyers V., Tahoori M., Demirdag Z., Sikal MB., Nassar H., Khdr H., Henkel J., Wolters C., van Kempen P., Geier J., Schlichtmann U., Sesli B., Sabih M., Wittmann J., Hannig F., Teich J., Steiner L., Wehn N., Shelkamy Ali M., Schmitz P., Kunz W., Kögler S., Sigl G.:
Multi-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAI
Conference on Design, Automation and Test in Europe (DATE) (Verona, 20. April 2026 - 22. April 2026)
In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2026
DOI: 10.23919/DATE69613.2026.11539555
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DI-EDAI

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PD Dr.-Ing. Frank Hannig

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Prof. Dr.-Ing. Jürgen Teich

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