DI-EDAI
Neural Approximate Accelerator Architecture Optimization for DNN Inference on Lightweight FPGAs
DI-EDAI
Neural Approximate Accelerator Architecture Optimization for DNN Inference on Lightweight FPGAs
Motivation
Chip design is the essential step when developing microelectronics for specific products and applications. Competence in chip design can strengthen Germany's innovation and competitiveness and increase its technological sovereignty in Europe. In order to leverage this potential, the German and European chip design ecosystem is to be expanded. To this end, the BMBF has launched the Microelectronics Design Initiative with four key areas of focus: a strong network as a central exchange platform, training and further education for talented individuals and specialists, research projects to strengthen design capabilities, and expanding research structures.
Project Goals
The aim of the project is to develop modern AI chips that are designed with a particular focus on security, trustworthiness, and energy efficiency in various application scenarios. Another goal is to implement a seamless transition from software-based AI algorithm development to efficient hardware implementation. The focus here is on the close linking of AI and hardware in the design process as well as the development of various AI accelerators and corresponding architectures. The end result should be an automated design methodology that extends from the AI software to the AI hardware.
The focus of our chair within DI-EDAI is, in particular, on the development of a co-exploration approach that optimizes both neural network models and associated AI-specific microprocessor extensions, taking into account non-functional requirements (e.g., cost, speed, accuracy, energy, security). The results, in the form of hardware blocks and EDA software, shall be published as open source and contribute to creating an ecosystem for designing sustainable and transparent AI systems.