• 930414C6
• 0000-0003-3663-6484

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Curriculum Vitæ

1974	born in Verl, Germany
2000	Diploma degree in EE/CS (interdisciplinary course of study), University of Paderborn, Germany
11/2000 – 12/2002	Researcher at the Computer Engineering Laboratory (Institute DATE), University of Paderborn
since 01/2003	Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
since 2004	Head of the Architecture and Compiler Design Group at the Department of Computer Science 12 (Hardware-Software-Co-Design), Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany
08/2009	Dr.-Ing. degree in CS, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany, Thesis: “Scheduling Techniques for High-Throughput Loop Accelerators”
07/2018	Habilitation (Dr.-Ing. habil.), Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen, Germany, Thesis: “Domain-specific and Resource-aware Computing“

Experience

C-LAB, Paderborn, Germany 01/1997 – 04/1999	Working student at C-LAB (Cooperative Computing & Communication Laboratory) in the research of analysing crosstalk noise problems during the design of digital high-speed integrated circuits
Electrolux, Fredericia, Denmark 04/1999 – 09/1999	Practical training at Electrolux GPDH Tech-Centre, primary development, hardware/software co-design of electrical hobs
C-LAB, Paderborn, Germany 10/1999 – 04/2000	Working student at C-LAB in the research group OIT (Optical Interconnection Technology)

Professional Scientific Activities

Recent and Upcoming Events

• SLOHA 2021 – General Co-Chair
  DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures, co-located with Conference on Design, Automation and Test in Europe (DATE), Virtual Workshop, February 5, 2021
• ARC 2021 – Programme Chair
  International Symposium on Applied Reconfigurable Computing (ARC), Rennes, France, June 29 – July 1, 2021
• Euro-Par 2021 – Global Chair Topic 1: Compilers, Tools and Environments
  27th International European Conference on Parallel and Distributed Computing (Euro-Par), Lisbon, Portugal, August 30 – September 3, 2021
• ASAP 2020 – Program Co-Chair
  31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Manchester, UK, July 6-8, 2020
• Associate Editor
  Journal of Real-Time Image Processing – Springer

Conference and Workshop Organization

• Local Arrangement and ICT Co-Chair, DATE 2019 – Conference on Design, Automation and Test in Europe
• Topic Chair E2: Compilers and Software Synthesis, DATE 2018 – Conference on Design, Automation and Test in Europe
• Topic Chair E2: Compilers and Software Synthesis for Embedded Systems, DATE 2017 – Conference on Design, Automation and Test in Europe
• Program Chair, ARCS 2016 – 29th GI/ITG International Conference on Architecture of Computing Systems
• Topic Co-Chair E2: Compilers and Software Synthesis for Embedded Systems, DATE 2016 – Conference on Design, Automation and Test in Europe
• General Co-Chair, FSP 2015 – Second International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
• Initiator and General Co-Chair, HIS 2015 – DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems, co-located with Conference on Design, Automation and Test in Europe (DATE)
• Initiator and General Co-Chair, FSP 2014 – First International Workshop on FPGAs for Software Programmers, co-located with International Conference on Field Programmable Logic and Applications (FPL)
• Co-Organizer and Program Chair, Racing 2014 – Workshop on Resource-Awareness and Adaptivity in Multi-Core Computing, co-located with IEEE European Test Symposium (ETS)
• Publication Chair, ASAP 2011 – 21th IEEE International Conference on Application-specific Systems, Architectures and Processors
• Publication Chair, ASAP 2010 – 21th IEEE International Conference on Application-specific Systems, Architectures and Processors
• Organization Assistance, CODES+ISSS 2007 – International Conference on Hardware-Software Codesign and System Synthesis
• Organization Assistance, Euro-Par 2006 – European Conference on Parallel Computing
• Organization Assistance, ARCS 2006 – 19th International Conference on Architecture of Computing Systems

Program Committee Member

Reviewing — Journals

• ACM TECS – ACM Transactions on Embedded Computing Systems
• ACM TACO – ACM Transactions on Architecture and Code Optimization
• ACM TODAES – ACM Transactions on Design Automation of Electronic Systems
• IEEE SPM – IEEE Signal Processing Magazine
• IEEE TVLSI – IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• IEEE TSP – IEEE Transactions on Signal Processing
• IEEE TCAD – IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• IEEE Design & Test – IEEE Design & Test of Computers
• EURASIP Journal on Embedded Systems
• Microprocessors and Microsystems

Reviewing — Conferences, Symposia, and Workshops (selection, in addition to TPC memberships)

• DAC (expert reviewer), ICCAD, CASES, SAMOS, ARCS, FPT, FPL, RAW, PARELEC, SiPS

Memberships

• Member of the IEEE since 2001 and Senior Member since 2012
• Affiliate member of the European Network of Excellence (NoE) on High Performance and Embedded Architecture and Compilation (HiPEAC)
• Member of the HiPEAC Reconfigurable Computing Cluster

Research Projects

Ongoing

• InvasIC: DFG Transregional Collaborative Research Centre 89 — Invasive Computing
• ExaStencils: Advanced Stencil-Code Engineering within the DFG Priority Programme 1648 (Software for Exascale Computing)
• HBS: DFG Research Training Group (Graduiertenkolleg) 1773 Heterogeneous Image Systems, Project B3
• INI.FAU: Parallelization and Resource Estimation of Algorithms for Heterogeneous DAS Architectures
• PARO: Architecture/Compiler Co-Design of Massively Parallel Processor Architectures
• MAP: Multi-core Architectures and Programming

Open Source Projects

• HIPAcc: A Domain-Specific Language and Compiler for Image Processing Applications

Completed

• MMSys: Motion Management System
• CoMap: Co-Design of Massively Parallel Embedded Processor Architectures
• DFG SFB 376 — Massively Parallel Computation
• BUILDABONG: Architecture and Compiler Design for ASIPs

Education

Lectures

• Domain-Specific and Resource-Aware Computing on Multicore Architectures
• Parallel Systems
• Embedded Systems

Exercises

• Domain-Specific and Resource-Aware Computing on Multicore Architectures
• Parallel Systems
• Embedded Systems
• Hardware-Software-Co-Design
• Architecture and Design of Embedded Systems (University of Paderborn)

Seminars

• Electronic System Level Design
• Multi-Core Architectures and Programming
• Oberseminar: Hardware-Software-Co-Design
• Energy Efficient Systems
• Bluetooth (University of Paderborn)

Labs

• Unix Basics (University of Paderborn)
• Architecture Synthesis (University of Paderborn)

Publications

Statistics

• h-index (Web of Science): 14
• h-index (Scopus): 19
• h-index (Google Scholar): 27
• Erdös Number: 3 (via this path: Frank Hannig → Sándor P. Fekete → Aviezri S. Fraenkel → Paul Erdös)