Frank Hannig

2025

• Groth S., Heidorn C., Schmid M., Teich J., Hannig F.:
  Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units
  28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Rostock, 11. March 2025 - 12. March 2025)
  In: Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2025
  BibTeX: Download
• Hernandez Morales JJ., Hannig F., Teich J.:
  A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices
  38th GI/ITG International Conference on Architecture of Computing Systems (Kiel, 22. April 2025 - 24. April 2025)
  In: Architecture of Computing Systems, 38th International Conference, ARCS 2025, Kiel, Germany, April 22–24, 2025, Proceedings 2025
  BibTeX: Download
• Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
  Europractice activity report 2024
  (2025), p. 29-30
  URL: https://europractice-ic.com/wp-content/uploads/2025/03/Europractice_ActivityReport2024_webversion.pdf
  BibTeX: Download
  (Techreport)
• Walter D., Halm M., Seidel D., Ghosh I., Heidorn C., Hannig F., Teich J.:
  Evaluation of CGRA Toolchains
  1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) (Lyon, 31. March 2025 - 2. April 2025)
  In: In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) 2025
  DOI: 10.48550/arXiv.2502.19114
  BibTeX: Download

2024

• Deutel M., Hannig F., Mutschler C., Teich J.:
  Fused-Layer CNNs for Memory-Efficient Inference on Microcontrollers
  Workshop on Machine Learning and Compression @ NeurIPS 2024 (Vancouver Convention Center, 10. December 2024 - 15. December 2024)
  Open Access: https://openreview.net/forum?id=2O8qbyxH6X
  BibTeX: Download
• Deutel M., Hannig F., Mutschler C., Teich J.:
  On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers
  In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44 (2024), p. 1250 - 1261
  ISSN: 0278-0070
  DOI: 10.1109/TCAD.2024.3484354
  URL: https://ieeexplore.ieee.org/document/10726519
  BibTeX: Download
• Groth S., Schmid M., Teich J., Hannig F.:
  Estimating the Execution Time of CNN Inference on GPUs
  27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. February 2024 - 15. February 2024)
  In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
  BibTeX: Download
• Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
  Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers
  10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Angers, 2. May 2024 - 4. May 2024)
  DOI: 10.5220/0000186800003702
  BibTeX: Download
• Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
  OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
  In: The Computing Research Repository (CoRR), 2024
  DOI: 10.48550/arXiv.2404.15833
  URL: https://arxiv.org/abs/2404.15833
  BibTeX: Download
  (online publication)
• Heidorn C., Hannig F., Riedelbauch D., Strohmeyer C., Teich J.:
  OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
  2024 Stuttgart International Symposium on Automotive and Engine Technology (Stuttgart, 2. July 2024 - 3. July 2024)
  In: André Casal Kulzer, Hans-Christian Reuss, Andreas Wagner (ed.): Proceeding of the 2024 Stuttgart International Symposium on Automotive and Engine Technology, Wiesbaden: 2024
  DOI: 10.1007/978-3-658-45018-2_4
  BibTeX: Download
• Heidorn C., Sabih M., Meyerhöfer N., Schinabeck C., Teich J., Hannig F.:
  Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks
  In: International Journal of Parallel Programming 52 (2024), p. 40 - 58
  ISSN: 0885-7458
  DOI: 10.1007/s10766-024-00760-5
  BibTeX: Download
• Plagwitz P., Hannig F., Teich J., Keszöcze O.:
  Compiler-based Processor Network Generation for Neural Networks on FPGAs
  27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (Kaiserslautern, 14. February 2024 - 15. February 2024)
  In: Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) 2024
  BibTeX: Download
• Plagwitz P., Hannig F., Teich J., Keszöcze O.:
  DSL-based SNN Accelerator Design using Chisel
  27th Euromicro Conference Series on Digital System Design (DSD) (Paris, 27. August 2024 - 30. August 2024)
  In: Proceedings of the 27th Euromicro Conference on Digital Systems Design (DSD) 2024
  DOI: 10.1109/DSD64264.2024.00032
  BibTeX: Download
• Plagwitz P., Hannig F., Teich J., Keszöcze O.:
  SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation
  20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) (Aveiro, 20. March 2024 - 22. March 2024)
  In: Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC) 2024
  DOI: 10.1007/978-3-031-55673-9_1
  BibTeX: Download
• Sabih M., Karim A., Wittmann J., Hannig F., Teich J.:
  Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
  International Conference on Field Programmable Technology (FPT 2024) (Sydney, Australia, 10. December 2024 - 12. December 2024)
  BibTeX: Download
• Sabih M., Sesli B., Hannig F., Teich J.:
  Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units
  Conference on Design, Automation and Test in Europe (DATE) (Valencia, 25. March 2024 - 27. March 2024)
  In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2024
  BibTeX: Download
• Walter D., Adamtschuk T., Hannig F., Teich J.:
  Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays
  35th IEEE International Conference on Application-specific Systems, Architectures and Processors (Hong Kong, 24. July 2024 - 26. July 2024)
  In: Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024
  DOI: 10.1109/ASAP61560.2024.00029
  URL: https://ieeexplore.ieee.org/document/10631126
  BibTeX: Download
• Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
  ALPACA: An Accelerator Chip for Nested Loop Programs
  IEEE International Symposium on Circuits and Systems (ISCAS) (Singapore, 19. May 2024 - 22. May 2024)
  In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2024
  DOI: 10.1109/ISCAS58744.2024.10558549
  URL: https://ieeexplore.ieee.org/document/10558549
  BibTeX: Download

2023

• Plagwitz P., Hannig F., Teich J., Keszöcze O.:
  To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations
  (2023)
  Open Access: https://arxiv.org/abs/2306.12742
  URL: https://arxiv.org/abs/2306.12742
  BibTeX: Download
  (online publication)
• Sabih M., Yayla M., Hannig F., Teich J., Chen JJ.:
  Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods
  EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and Systems (Rome, Italy, 8. May 2023 - 8. May 2023)
  In: Eiko Yoneki, Luigi Nardi (ed.): EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and System, New York(NY) United States: 2023
  DOI: 10.1145/3578356.3592595
  URL: https://dl.acm.org/doi/10.1145/3578356.3592595
  BibTeX: Download

2022

• Anantharajaiah N., Asfour T., Bader M., Bauer L., Becker J., Bischof S., Brand M., Bungartz HJ., Eichler C., Esper K., Falk J., Fasfous N., Freiling F., Fried A., Gerndt M., Glaß M., Gonzalez J., Hannig F., Heidorn C., Henkel J., Herkersdorf A., Herzog B., John J., Hönig T., Hundhausen F., Khdr H., Langer T., Lenke O., Lesniak F., Lindermayr A., Listl A., Maier S., Megow N., Mettler M., Müller-Gritschneder D., Nassar H., Paus F., Pöppl A., Pourmohseni B., Rabenstein J., Raffeck P., Rapp M., Rivas SN., Sagi M., Schirrmacher F., Schlichtmann U., Schmaus F., Schröder-Preikschat W., Schwarzer T., Sikal MB., Simon B., Snelting G., Spieck J., Srivatsa A., Stechele W., Teich J., Comprés Ureña IA., Verbauwhede I., Walter D., Wild T., Wildermann S., Wille M., Witterauf M., Zhang L.:
  Invasive Computing
  FAU University Press, 2022
  ISBN: 978-3-96147-571-1
  DOI: 10.25593/978-3-96147-571-1
  BibTeX: Download
• Becker J., Hannig F., Wild T., Brand M., Lenke O., Lesniak F.:
  Validation and Demonstrator
  In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 411-431
  ISBN: 978-3-96147-571-1
  DOI: 10.25593/978-3-96147-571-1
  BibTeX: Download
• Brand M., Keszöcze O., Teich J.:
  Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview
  In: IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2022), p. 2661 - 2666
  ISSN: 1057-7130
  DOI: 10.1109/TCSII.2022.3173753
  BibTeX: Download
• Hannig F., Derrien S.:
  Special Issue on Applied Reconfigurable Computing
  In: Journal of Signal Processing Systems (2022)
  ISSN: 1939-8018
  DOI: 10.1007/s11265-022-01806-y
  BibTeX: Download
• Heidorn C., Meyerhöfer N., Schinabeck C., Hannig F., Teich J.:
  Hardware-Aware Evolutionary Filter Pruning
  International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (Pythagoreio, Samos, 3. July 2022 - 7. July 2022)
  DOI: 10.1007/978-3-031-15074-6_18
  BibTeX: Download
• Mishra A., Hannig F., Teich J., Sabih M.:
  MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks
  The 13th International Green and Sustainable Computing Conference (IGSC) (Virtual, 24. October 2022 - 27. October 2022)
  In: IEEE (ed.): 2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC), Pittsburgh, PA, USA: 2022
  DOI: 10.1109/IGSC55832.2022.9969363
  URL: https://ieeexplore.ieee.org/document/9969374
  BibTeX: Download
• Plagwitz P., Hannig F., Teich J.:
  TRAC: Compilation-based Design of Transformer Accelerators for FPGAs
  International Conference on Field Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
  In: IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications 2022
  DOI: 10.1109/FPL57034.2022.00015
  BibTeX: Download
• Sabih M., Hannig F., Teich J.:
  DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks
  2nd European Workshop on Machine Learning and Systems (EuroMLSys) (Rennes, France, 5. April 2022 - 8. April 2022)
  In: Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys), New York, NY, United States: 2022
  DOI: 10.1145/3517207.3526982
  BibTeX: Download
• Snelting G., Teich J., Fried A., Hannig F., Witterauf M.:
  Compilation and Code Generation for Invasive Programs
  In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 309-333
  ISBN: 978-3-96147-571-1
  DOI: 10.25593/978-3-96147-571-1
  BibTeX: Download
• Teich J., Brand M., Hannig F., Heidorn C., Walter D., Witterauf M.:
  Invasive Tightly-Coupled Processor Arrays
  In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (ed.): Invasive Computing, FAU University Press, 2022, p. 177-202
  ISBN: 978-3-96147-571-1
  DOI: 10.25593/978-3-96147-571-1
  BibTeX: Download

2021

• Alhaddad S., Förstner J., Groth S., Grünewald D., Grynko Y., Hannig F., Kenter T., Pfreundt FJ., Plessl C., Schotte M., Steinke T., Teich J., Weiser M., Wende F.:
  HighPerMeshes -- A Domain-Specific Language for Numerical Algorithms on Unstructured Grids
  18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) (Warsaw, 24. August 2020 - 24. August 2020)
  In: Proceedings of the 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2020: Parallel Processing Workshops 2021
  DOI: 10.1007/978-3-030-71593-9_15
  BibTeX: Download
• Alhaddad S., Förstner J., Groth S., Grünewald D., Grynko Y., Hannig F., Kenter T., Pfreundt FJ., Plessl C., Schotte M., Steinke T., Teich J., Weiser M., Wende F.:
  The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids
  In: Concurrency and Computation-Practice & Experience (2021)
  ISSN: 1532-0626
  DOI: 10.1002/cpe.6616
  BibTeX: Download
• Derrien S., Hannig F., Diniz PC., Chillet D.:
  Applied Reconfigurable Computing. Architectures, Tools, and Applications
  17th International Symposium on Applied Reconfigurable Computing 2021 (Virtual Event, 29. June 2021 - 30. June 2021)
  In: Applied Reconfigurable Computing. Architectures, Tools, and Applications 2021
  DOI: 10.1007/978-3-030-79025-7
  BibTeX: Download
• Groth S., Teich J., Hannig F.:
  Efficient Application of Tensor Core Units for Convolving Images
  24th International Workshop on Software and Compilers for Embedded Systems (Eindhoven (NL), 1. November 2021 - 2. November 2021)
  In: Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems 2021
  DOI: 10.1145/3493229.3493305
  BibTeX: Download
• Hannig F., Koch D.:
  Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors
  In: Journal of Signal Processing Systems (2021)
  ISSN: 1939-8018
  DOI: 10.1007/s11265-021-01708-5
  BibTeX: Download
• Hannig F., Meloni P., Spallanzani M., Ziegler M. (ed.):
  Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021)
  2021
  Open Access: http://arxiv.org/html/2102.00818
  URL: http://arxiv.org/abs/2102.00818
  BibTeX: Download
• Hannig F., Teich J.:
  Open Source Hardware
  In: IEEE Computer 54 (2021), p. 111-115
  ISSN: 0018-9162
  DOI: 10.1109/MC.2021.3099046
  BibTeX: Download
• Heidorn C., Walter D., Candir YE., Hannig F., Teich J.:
  Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
  31st International Conference on Field Programmable Logic and Applications (FPL) (Virtual Conference, 30. August 2021 - 3. September 2021)
  In: Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL) 2021
  DOI: 10.1109/FPL53798.2021.00079
  BibTeX: Download
• Plagwitz P., Hannig F., Ströbel M., Strohmeyer C., Teich J.:
  A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
  29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Virtual Conference, 9. May 2021 - 12. May 2021)
  In: Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2021
  DOI: 10.1109/FCCM51124.2021.00010
  URL: https://ieeexplore.ieee.org/document/9444092
  BibTeX: Download
• Qiao B., Teich J., Hannig F.:
  An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning
  2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (Portland, OR, 17. May 2021 - 21. May 2021)
  In: Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) 2021
  DOI: 10.1109/IPDPSW52791.2021.00067
  BibTeX: Download
• Sabih M., Hannig F., Teich J.:
  Fault-Tolerant Low-Precision DNNs using Explainable AI
  Workshop on Dependable and Secure Machine Learning (DSML) (Virtual Workshop, 21. June 2021 - 24. June 2021)
  In: 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) 2021
  DOI: 10.1109/DSN-W52860.2021.00036
  URL: https://ieeexplore.ieee.org/document/9502445/
  BibTeX: Download
• Witterauf M., Walter D., Hannig F., Teich J.:
  Symbolic Loop Compilation for Tightly Coupled Processor Arrays
  In: ACM Transactions on Embedded Computing Systems (2021)
  ISSN: 1539-9087
  DOI: 10.1145/3466897
  BibTeX: Download
• Özkan MA., Ok B., Qiao B., Teich J., Hannig F.:
  HipaccVX: Wedding of OpenVX and DSL-based Code Generation
  In: Journal of Real-Time Image Processing 18 (2021), p. 765 - 777
  ISSN: 1861-8200
  DOI: 10.1007/s11554-020-01015-5
  URL: http://link.springer.com/article/10.1007/s11554-020-01015-5
  BibTeX: Download

2020

• Arvind TKR., Brand M., Heidorn C., Boppu S., Hannig F., Teich J.:
  Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats
  24th International Symposium on VLSI Design and Test (VDAT) (Bhubaneswar, 23. July 2020 - 25. July 2020)
  In: Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT) 2020
  DOI: 10.1109/VDAT50263.2020.9190305
  BibTeX: Download
• Groth S., Grünewald D., Teich J., Hannig F.:
  A Runtime System for Finite Element Methods in a Partitioned Global Address Space
  ACM International Conference on Computing Frontiers 2020 (Catania, Sicily, Italy, 11. May 2020 - 13. May 2020)
  In: Proceedings of the 17th ACM International Conference on Computing Frontiers (CF) 2020
  DOI: 10.1145/3387902.3392628
  BibTeX: Download
• Hannig F., Navaridas J., Koch D., Abdelhadi A. (ed.):
  Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
  2020
  ISBN: 978-1-7281-7147-0
  DOI: 10.1109/ASAP49362.2020
  BibTeX: Download
• Heidorn C., Hannig F., Teich J.:
  Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs
  International Workshop on Software and Compilers for Embedded Systems (SCOPES) (St. Goar, 25. May 2020 - 26. May 2020)
  In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
  DOI: 10.1145/3378678.3391878
  BibTeX: Download
• Lengauer C., Apel S., Bolten M., Chiba S., Rüde U., Teich J., Größlinger A., Hannig F., Köstler H., Claus L., Grebhahn A., Groth S., Kronawitter S., Kuckuk S., Rittich H., Schmitt C., Schmitt J.:
  ExaStencils: Advanced multigrid solver generation
  In: Hans-Joachim Bungartz, Severin Reiz, Benjamin Uekermann, Philipp Neumann, Wolfgang E. Nagel (ed.): Lecture notes in computational science and engineering, Cham: Springer, 2020, p. 405-452 (Software for Exascale Computing SPPEXA 2016 – 2019, Vol.136)
  ISBN: 978-3-030-47955-8
  DOI: 10.1007/978-3-030-47956-5
  URL: https://library.oapen.org/bitstream/handle/20.500.12657/41289/2020_Book_SoftwareForExascaleComputing-S.pdf?sequence=1#page=411
  BibTeX: Download
• Lengauer C., Apel S., Bolten M., Chiba S., Rüde U., Teich J., Größlinger A., Hannig F., Köstler H., Claus L., Grebhahn A., Groth S., Kronawitter S., Kuckuk S., Rittich H., Schmitt C., Schmitt J.:
  ExaStencils – Advanced Multigrid Solver Generation
  In: Hans-Joachim Bungartz, Severin Reiz, Philipp Neumann, Benjamin Uekermann, Wolfgang Nagel (ed.): Software for Exascale Computing – SPPEXA 2016-2019, Springer, 2020, p. 405-452 (Lecture Notes in Computer Science and Engineering, Vol.136)
  ISBN: 978-3-030-47955-8
  DOI: 10.1007/978-3-030-47956-5_14
  URL: https://www12.cs.fau.de/downloads/hannig/publications/ExaStencils_Advanced_Multigrid_Solver_Generation.pdf
  BibTeX: Download
• Mattauch S., Lohmann K., Hannig F., Lohmann D., Teich J.:
  A Bibliometric Approach for Detecting the Gender Gap in Computer Science
  In: Communications of the ACM 63 (2020), p. 39-45
  ISSN: 0001-0782
  DOI: 10.1145/3376901
  BibTeX: Download
• Qiao B., Reiche O., Teich J., Hannig F.:
  Unveiling Kernel Concurrency in Multiresolution Filters on GPUs with an Image Processing DSL
  13th Workshop on General Purpose Processing Using GPU (GPGPU) (San Diego, CA, USA, 23. February 2020 - 23. February 2020)
  In: Proceedings of the 13th Workshop on General Purpose Processing Using GPU (GPGPU) 2020
  DOI: 10.1145/3366428.3380773
  BibTeX: Download
• Qiao B., Reiche O., Özkan MA., Teich J., Hannig F.:
  Efficient Parallel Reduction on GPUs with Hipacc
  23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 25. May 2020 - 26. May 2020)
  In: Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
  DOI: 10.1145/3378678.3391885
  BibTeX: Download
• Qiao B., Özkan MA., Teich J., Hannig F.:
  The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL
  57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. July 2020 - 23. July 2020)
  In: Proceedings of the 57th Annual Design Automation Conference (DAC) 2020
  DOI: 10.1109/DAC18072.2020.9218531
  BibTeX: Download
• Sabih M., Hannig F., Teich J.:
  Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks
  (2020)
  Open Access: https://arxiv.org/pdf/2008.09072
  URL: https://arxiv.org/abs/2008.09072
  BibTeX: Download
  (online publication)
• Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Leißa R., Hack S., Teich J., Hannig F.:
  AnyHLS: High-Level Synthesis with Partial Evaluation
  International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (Hamburg, 20. September 2020 - 25. September 2020)
  DOI: 10.1109/tcad.2020.3012172
  URL: https://arxiv.org/pdf/2002.05796.pdf
  BibTeX: Download
• Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Leißa R., Hack S., Teich J., Hannig F.:
  AnyHLS: High-Level Synthesis with Partial Evaluation
  In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 (2020), p. 3202-3214
  ISSN: 0278-0070
  DOI: 10.1109/TCAD.2020.3012172
  URL: https://arxiv.org/pdf/2002.05796.pdf
  BibTeX: Download

2019

• Brand M., Witterauf M., Hannig F., Teich J.:
  Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic
  ACM International Conference on Computing Frontiers 2019 (Alghero, Sardinia, 30. April 2019 - 2. May 2019)
  DOI: 10.1145/3310273.3322833
  BibTeX: Download
• Brand M., Witterauf M., Sousa É., Tanase AP., Hannig F., Teich J.:
  *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing
  In: Concurrency and Computation-Practice & Experience (2019)
  ISSN: 1532-0626
  DOI: 10.1002/cpe.5149
  BibTeX: Download
• Fickenscher J., Hannig F., Teich J.:
  DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs
  ARCS 2019 - 32nd International Conference on Architecture of Computing Systems (Copenhagen, 20. May 2019 - 23. May 2019)
  In: Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck (ed.): Proceedings of the 32nd International Conference on Architecture of Computing Systems (ARCS) 2019
  DOI: 10.1007/978-3-030-18656-2
  BibTeX: Download
• Groth S., Schmitt C., Teich J., Hannig F.:
  SYCL Code Generation for Multigrid Methods
  22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) (Sankt Goar, Germany, 27. May 2019 - 29. May 2019)
  In: 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES '19) 2019
  DOI: 10.1145/3323439.3323984
  BibTeX: Download
• Heidorn C., Witterauf M., Hannig F., Teich J.:
  Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays
  In: Journal of Computers 14 (2019), p. 541-556
  ISSN: 1796-203X
  DOI: 10.17706/jcp.14.8.541-556
  BibTeX: Download
• Membarth R., Dutta H., Hannig F., Teich J.:
  Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards
  In: Transactions on High-Performance Embedded Architectures and Compilers V, Springer, 2019, p. 1-20 (Lecture Notes in Computer Science (LNCS), Vol.11225)
  ISBN: 978-3-662-58833-8
  DOI: 10.1007/978-3-662-58834-5_1
  BibTeX: Download
• Qiao B., Reiche O., Hannig F., Teich J.:
  From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization
  2019 International Symposium on Code Generation and Optimization (CGO) (Washington, DC, USA, 16. February 2019 - 20. February 2019)
  In: Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO) 2019
  DOI: 10.1109/CGO.2019.8661176
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  ActorX10 and Run-Time Application Embedding
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 129-164 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_6
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Fundamentals
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 9-40 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_2
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Hybrid Network-on-Chip Simulation
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 77-99 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_4
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Introduction
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 1-7 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_1
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 41-76 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_3
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Modeling and Simulation of Invasive Applications and Architectures
  Singapore: Springer, 2019
  (Computer Architecture and Design Methodologies)
  ISBN: 978-981-13-8386-1
  DOI: 10.1007/978-981-13-8387-8
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Modeling and Simulation of Invasive Applications and Architectures Conclusions and Future Directions
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 165-168 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_7
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Parallel MPSoC Simulation and Architecture Evaluation
  In: Sascha Roloff, Frank Hannig, Jürgen Teich (ed.): Modeling and Simulation of Invasive Applications and Architectures, 2019, p. 101-128 (Computer Architecture and Design Methodologies)
  DOI: 10.1007/978-981-13-8387-8_5
  BibTeX: Download
• Witterauf M., Hannig F., Teich J.:
  Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays
  International Conference on Formal Methods and Models for System Design (MEMOCODE) (San Diego, 9. October 2019 - 11. October 2019)
  In: Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE) 2019
  BibTeX: Download
• Özkan MA., Reiche O., Qiao B., Membarth R., Teich J., Hannig F.:
  Synthesizing High-Performance Image Processing Applications with Hipacc
  Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Florence, 25. March 2019 - 29. March 2019)
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/date-ubooth19.pdf
  BibTeX: Download
  (online publication)

2018

• Afzal A., Schmitt C., Alhaddad S., Grynko Y., Teich J., Förstner J., Hannig F.:
  Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study
  The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Politecnico di Milano, Milan, 10. July 2018 - 12. July 2018)
  In: Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018
  DOI: 10.1109/ASAP.2018.8445127
  URL: https://www12.cs.fau.de/downloads/schmittch/publications/ASAGTFH18asap.pdf
  BibTeX: Download
• Fey D., Hannig F.:
  Special Issue on Heterogeneous Real-Time Image Processing
  In: Journal of Real-Time Image Processing 14 (2018), p. 513-515
  ISSN: 1861-8200
  DOI: 10.1007/s11554-018-0763-2
  BibTeX: Download
• Fickenscher J., Hannig F., Bouzouraa ME., Teich J.:
  Embedded GPUs in Future Automated Cars
  Design, Automation and Test in Europe (DATE) (Dresden, 19. March 2018 - 23. March 2018)
  BibTeX: Download
  (Working Paper)
• Fickenscher J., Hannig F., Teich J., Bouzouraa ME.:
  Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs
  4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) (Funchal, Madeira, Portugal, 16. March 2018 - 18. March 2018)
  DOI: 10.5220/0006677302980306
  BibTeX: Download
• Fickenscher J., Schlumberger J., Hannig F., Bouzouraa ME., Teich J.:
  Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs
  Design, Automation and Test in Europe (DATE) (Dresden, Germany, 19. March 2018 - 23. March 2018)
  DOI: 10.23919/DATE.2018.8342050
  BibTeX: Download
• Fickenscher J., Schmidt S., Hannig F., Bouzouraa ME., Teich J.:
  Path Planning for Highly Automated Driving on Embedded GPUs
  4 (2018)
  ISSN: 2079-9268
  DOI: 10.3390/jlpea8040035
  BibTeX: Download
• Kenter T., Mahale G., Alhaddad S., Grynko Y., Schmitt C., Afzal A., Hannig F., Förstner J., Plessl C.:
  OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
  The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Boulder, CO, USA, 29. April 2018 - 1. May 2018)
  In: Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2018
  DOI: 10.1109/FCCM.2018.00037
  BibTeX: Download
• Mattauch S., Lohmann K., Hannig F., Lohmann D., Teich J.:
  The Gender Gap in Computer Science --- A Bibliometric Analysis
  (2018)
  ISSN: 2191-5008
  DOI: 10.25593/issn.2191-5008/CS-2018-02
  BibTeX: Download
  (Techreport)
• Qiao B., Reiche O., Hannig F., Teich J.:
  Automatic Kernel Fusion for Image Processing DSLs
  21st International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 28. May 2018 - 30. May 2018)
  In: Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2018
  DOI: 10.1145/3207719.3207723
  BibTeX: Download
• Reiche O., Özkan MA., Hannig F., Teich J., Schmid M.:
  Loop Parallelization Techniques for FPGA Accelerator Synthesis
  In: Journal of Signal Processing Systems 90 (2018), p. 3-27
  ISSN: 1939-8115
  DOI: 10.1007/s11265-017-1229-7
  BibTeX: Download
• Schmitt C., Hannig F., Teich J.:
  A Target Platform Description Language for Parallel Code Generation
  31st GI/ITG International Conference on Architecture of Computing Systems (ARCS) (Braunschweig, 9. April 2018 - 12. April 2018)
  In: Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS), Berlin: 2018
  URL: https://www12.cs.fau.de/downloads/schmittch/publications/SHT18arcs.pdf
  BibTeX: Download
• Schmitt C., Kronawitter S., Hannig F., Teich J., Lengauer C.:
  Automating the Development of High-Performance Multigrid Solvers
  In: Proceedings of the IEEE 106 (2018), p. 1969-1984
  ISSN: 0018-9219
  DOI: 10.1109/JPROC.2018.2854229
  BibTeX: Download
• Schmitt C., Schmid M., Kuckuk S., Köstler H., Teich J., Hannig F.:
  Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution
  In: Parallel Processing Letters 28 (2018), Article No.: 1850016
  ISSN: 0129-6264
  DOI: 10.1142/S0129626418500160
  BibTeX: Download
• Sousa É., Witterauf M., Brand M., Tanase AP., Hannig F., Teich J.:
  Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
  29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Milan, Italy, 10. July 2018 - 12. July 2018)
  DOI: 10.1109/ASAP.2018.8445109
  URL: https://ieeexplore.ieee.org/abstract/document/8445109/
  BibTeX: Download
• Tanase AP., Hannig F., Teich J.:
  Symbolic Parallelization of Nested Loop Programs
  Springer, 2018
  ISBN: 978-3-319-73908-3
  DOI: 10.1007/978-3-319-73909-0
  BibTeX: Download
• Özkan MA., Pérard-Gayot A., Membarth R., Slusallek P., Teich J., Hannig F.:
  A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement
  International Workshop on FPGAs for Software Programmers (Dublin, 31. August 2018)
  In: Proceedings of the Fifth International Workshop on FPGAs for Software Programmers 2018
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/fsp18.pdf
  BibTeX: Download

2017

• Brand M., Hannig F., Tanase AP., Teich J.:
  Efficiency in ILP Processing by Using Orthogonality
  The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017) (Seattle, 10. July 2017 - 12. July 2017)
  In: IEEE (ed.): 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
  DOI: 10.1109/ASAP.2017.7995282
  BibTeX: Download
• Brand M., Hannig F., Tanase AP., Teich J.:
  Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
  IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17) (Korea University, Seoul, Korea, 18. September 2017 - 20. September 2017)
  In: 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip 2017
  DOI: 10.1109/MCSoC.2017.17
  BibTeX: Download
• Fickenscher J., Bouzouraa ME., Hannig F., Teich J.:
  Environment Mapping Using Massively Parallel Architectures
  Vehicle Intelligence (München, 5. December 2017 - 7. December 2017)
  BibTeX: Download
• Fickenscher J., Reinhart S., Bouzouraa ME., Hannig F., Teich J.:
  Convoy Tracking for ADAS on Embedded GPUs
  Intelligent Vehicles Symposium (IV 2017) (Redondo Beach, CA, USA, 11. June 2017 - 14. June 2017)
  BibTeX: Download
• Hannig F.:
  Domain-specific and Resource-aware Computing (Habilitation, 2017)
  DOI: 10.13140/RG.2.2.23418.13761
  URL: https://www.cs12.tf.fau.de/files/2016/08/Frank_Hannig_Habilitation2017.pdf
  BibTeX: Download
• Khdr H., Pagani S., Rodrigues Sousa E., Lari V., Pathania A., Hannig F., Shafique M., Teich J., Henkel J.:
  Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
  In: IEEE Transactions on Computers 66 (2017), p. 488--501
  ISSN: 0018-9340
  DOI: 10.1109/TC.2016.2595560
  BibTeX: Download
• Köstler H., Schmitt C., Kuckuk S., Kronawitter S., Hannig F., Teich J., Rüde U., Lengauer C.:
  A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms
  In: International Journal of Computational Science and Engineering 14 (2017), p. 150-163
  ISSN: 1742-7185
  DOI: 10.1504/IJCSE.2017.10003829
  BibTeX: Download
• Reiche O., Kobylko C., Hannig F., Teich J.:
  Auto-vectorization for Image Processing DSLs
  18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (Barcelona, 21. June 2017 - 22. June 2017)
  In: Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) 2017
  DOI: 10.1145/3078633.3081039
  BibTeX: Download
• Reiche O., Özkan MA., Membarth R., Teich J., Hannig F.:
  Generating FPGA-based Image Processing Accelerators with Hipacc
  International Conference on Computer Aided Design (ICCAD) (Irvine, 13. November 2017 - 16. November 2017)
  In: Proceedings of the International Conference on Computer Aided Design (ICCAD) 2017
  DOI: 10.1109/ICCAD.2017.8203894
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  High Performance Network-on-Chip Simulation by Interval-based Timing Predictions
  15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (Seoul, Republic of Korea, 15. October 2017 - 20. October 2017)
  In: ACM (ed.): Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2017
  DOI: 10.1145/3139315.3139320
  BibTeX: Download
• Sousa É., Chakraborty A., Tanase AP., Hannig F., Teich J.:
  TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays
  Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, Mexico, 4. December 2017 - 6. December 2017)
  DOI: 10.1109/RECONFIG.2017.8279818
  URL: http://ieeexplore.ieee.org/document/8279818/
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays
  International Conference on ReConFigurable Computing and FPGA's (ReConFig) (Cancun, Mexico, 4. December 2017 - 6. December 2017)
  DOI: 10.1109/RECONFIG.2017.8279768
  URL: http://ieeexplore.ieee.org/document/8279768/
  BibTeX: Download
• Tanase AP., Witterauf M., Teich J., Hannig F.:
  Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
  In: ACM Transactions on Embedded Computing Systems 17 (2017), p. 31:1-31:27
  ISSN: 1539-9087
  DOI: 10.1145/3092952
  BibTeX: Download
• Unat D., Dubey A., Hoefler T., Shalf J., Abraham M., Bianco M., Chamberlain BL., Cledat R., Edwards HC., Finkel H., Fürlinger K., Hannig F., Jeannot E., Kamil A., Keasler J., Kelly PHJ., Leung VJ., Ltaief H., Maruyama N., Newburn C., Pericàs M.:
  Trends in Data Locality Abstractions for HPC Systems
  In: IEEE Transactions on Parallel and Distributed Systems (2017)
  ISSN: 1045-9219
  DOI: 10.1109/TPDS.2017.2703149
  BibTeX: Download
• Witterauf M., Hannig F., Teich J.:
  Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates
  Symposium on Rapid System Prototyping (Seoul, South Korea, 19. October 2017 - 20. October 2017)
  In: Proceedings of the Symposium on Rapid System Prototyping 2017
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis
  Fourth International Workshop on FPGAs for Software Programmers (FSP) (Ghent, 7. September 2017)
  In: Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP) 2017
  URL: https://ieeexplore.ieee.org/document/8084549
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
  28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Seattle, 10. July 2017 - 12. July 2017)
  In: 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
  DOI: 10.1109/ASAP.2017.7995273
  URL: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf
  BibTeX: Download

2016

• Bhadouria VS., Tanase AP., Schmid M., Hannig F., Teich J., Ghoshal D.:
  A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
  In: Journal of Signal Processing Systems 89 (2016), p. 225-242
  ISSN: 1939-8018
  DOI: 10.1007/s11265-016-1187-5
  BibTeX: Download
• Fickenscher J., Reiche O., Schlumberger J., Hannig F., Teich J.:
  Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs
  18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (Santa Cruz, CA, 7. October 2016 - 8. October 2016)
  In: Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) 2016
  DOI: 10.1109/HLDVT.2016.7748257
  BibTeX: Download
• Hannig F.:
  A Quick Tour of High-Level Synthesis Solutions for FPGAs
  In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016
  DOI: 10.1007/978-3-319-26408-0_3
  BibTeX: Download
• Hannig F., Cardoso J., Fey D., Schröder-Preikschat W., Teich J.:
  Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings
  Springer Verlag, 2016
  ISBN: 9783319306940
  DOI: 10.1007/978-3-319-30695-7
  BibTeX: Download
• Hannig F., Cardoso JMP., Pionteck T., Fey D., Schröder-Preikschat W., Teich J. (ed.):
  Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS)
  Berlin; Heidelberg: 2016
  (Lecture Notes in Computer Science (LNCS), Vol. 9637)
  ISBN: 978-3-319-30694-0
  DOI: 10.1007/978-3-319-30695-7
  BibTeX: Download
• Henkel J., Chen Q., Schmitt-Landsiedel D., Glocker E., Sousa É., Schlichtmann U., Herkersdorf A., Hannig F., Wenzel V., Wagner P., Sagi M., Wild T., Khdr H., Pagani S., Pathania A., Bauer L.:
  Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach
  In: it - Information Technology 58 (2016), p. 297-307
  ISSN: 1611-2776
  DOI: 10.1515/itit-2016-0028
  BibTeX: Download
• Häublein K., Reichenbach M., Reiche O., Özkan MA., Fey D., Hannig F., Teich J.:
  Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
  16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (Island of Samos, 18. June 2016 - 21. June 2016)
  In: Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2016
  DOI: 10.1109/SAMOS.2016.7818350
  BibTeX: Download
• Koch D., Hannig F., Ziener D. (ed.):
  FPGAs for Software Programmers
  Berlin; Heidelberg: 2016
  ISBN: 978-3-319-26406-6
  DOI: 10.1007/978-3-319-26408-0
  BibTeX: Download
• Koch D., Ziener D., Hannig F.:
  FPGA versus Software Programming - Why, When, and How?
  In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, 2016, p. 1-21
  DOI: 10.1007/978-3-319-26408-0_1
  BibTeX: Download
• Membarth R., Reiche O., Hannig F., Teich J., Körner M., Eckert W.:
  HIPAcc: A Domain-Specific Language and Compiler for Image Processing
  In: IEEE Transactions on Parallel and Distributed Systems 27 (2016), p. 210-224
  ISSN: 1045-9219
  DOI: 10.1109/TPDS.2015.2394802
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip
  Design, Automation and Test in Europe (DATE) (Dresden, 14. March 2016 - 18. March 2016)
  In: Tool presentation at the University Booth 2016
  URL: https://www.date-conference.com/system/files/file/date16/ubooth/37912.pdf
  BibTeX: Download
• Roloff S., Pöppl A., Schwarzer T., Wildermann S., Baader M., Glaß M., Hannig F., Teich J.:
  ActorX10: An Actor Library for X10
  ACM SIGPLAN X10 Workshop (X10), ACM (Santa Barbara, CA)
  In: Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) 2016
  BibTeX: Download
• Schmid M., Reiche O., Hannig F., Teich J.:
  HIPAcc
  In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016
  DOI: 10.1007/978-3-319-26408-0_12
  BibTeX: Download
• Schmid M., Schmitt C., Hannig F., Malazgirt GA., Sönmez N., Yurdakul A., Cristal A.:
  Big Data and HPC Acceleration with Vivado HLS
  In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016, p. 115-136
  DOI: 10.1007/978-3-319-26408-0_7
  BibTeX: Download
• Schmitt C., Kuckuk S., Hannig F., Teich J., Köstler H., Rüde U., Lengauer C.:
  Systems of Partial Differential Equations in ExaSlang
  In: Software for Exascale Computing - SPPEXA 2013-2015, Berlin, Heidelberg, New York: Springer, 2016, p. 47-67 (Lecture Notes in Computational Science and Engineering, Vol.113)
  ISBN: 9783319405261
  DOI: 10.1007/978-3-319-40528-5_3
  BibTeX: Download
• Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
  LoopInvader: A Compiler for Tightly Coupled Processor Arrays
  Design, Automation and Test in Europe (DATE) (Dresden, 14. March 2016 - 18. March 2016)
  In: Tool presentation at the University Booth 2016
  URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
  BibTeX: Download
• Witterauf M., Tanase AP., Hannig F., Teich J.:
  Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays
  IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (London, 6. July 2016 - 8. July 2016)
  In: Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016
  BibTeX: Download
• Özkan MA., Reiche O., Hannig F., Teich J.:
  FPGA-Based Accelerator Design from a Domain-Specific Language
  26th International Conference on Field-Programmable Logic and Applications (FPL) (Lausanne, 29. August 2016 - 2. September 2016)
  In: Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL) 2016
  DOI: 10.1109/FPL.2016.7577357
  BibTeX: Download

2015

• Gangadharan D., Sousa É., Lari V., Hannig F., Teich J.:
  Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms
  48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (Pacific Grove, CA, 2. November 2014 - 5. November 2014)
  In: Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) 2015
  DOI: 10.1109/ACSSC.2014.7094471
  BibTeX: Download
• Hannig F., Fey D., Lokhmotov A. (ed.):
  Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
  2015
  Open Access: http://arxiv.org/abs/1502.07241
  URL: http://arxiv.org/abs/1502.07241
  BibTeX: Download
• Hannig F., Herkersdorf A.:
  Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures
  In: Journal of Systems Architecture 61 (2015), p. 600
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.11.003
  BibTeX: Download
• Hannig F., Koch D., Ziener D. (ed.):
  Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
  2015
  BibTeX: Download
• Lari V., Tanase AP., Teich J., Witterauf M., Khosravi F., Hannig F., Meyer B.:
  A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays
  NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. June 2016 - 18. June 2015)
  In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
  DOI: 10.1109/AHS.2015.7231157
  BibTeX: Download
• Paul J., Stechele W., Oechslein B., Erhardt C., Schedel J., Lohmann D., Schröder-Preikschat W., Kröhnert M., Asfour T., Sousa É., Hannig F., Lari V., Teich J., Grudnitsky A., Bauer L., Henkel J.:
  Resource-awareness on heterogeneous MPSoCs for image processing
  In: Journal of Systems Architecture 61 (2015), p. 668-680
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.09.002
  BibTeX: Download
• Reiche O., Häublein K., Reichenbach M., Hannig F., Teich J., Fey D.:
  Automatic Optimization of Hardware Accelerators for Image Processing
  DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (Grenoble, 13. March 2015 - 13. March 2015)
  In: Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) 2015
  URL: http://arxiv.org/abs/1502.07448
  BibTeX: Download
• Reiche O., Häublein K., Reichenbach M., Schmid M., Hannig F., Teich J., Fey D.:
  Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
  In: Journal of Systems Architecture 61 (2015), p. 646-658
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2015.09.004
  URL: https://www12.cs.fau.de/downloads/reiche/publications/RHRSHTF15.pdf
  BibTeX: Download
• Roloff S., Schafhauser D., Hannig F., Teich J.:
  Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
  52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 (San Francisco, CA, 7. June 2015 - 11. June 2015)
  In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) 2015
  DOI: 10.1145/2744769.2744840
  BibTeX: Download
• Roloff S., Wildermann S., Hannig F., Teich J.:
  Invasive computing for predictable stream processing: A simulation-based case study
  13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2015 (Amsterdam, 8. October 2015 - 9. October 2015)
  DOI: 10.1109/ESTIMedia.2015.7351761
  BibTeX: Download
• Schmid M., Reiche O., Hannig F., Teich J.:
  Loop Coarsening in C-based High-Level Synthesis
  26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Toronto, 27. July 2015 - 29. July 2015)
  In: Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
  DOI: 10.1109/ASAP.2015.7245730
  URL: https://www12.cs.fau.de/downloads/reiche/publications/SRHT15.pdf
  BibTeX: Download
• Schmitt C., Schmid M., Hannig F., Teich J., Kuckuk S., Köstler H.:
  Generation of Multigrid-based Numerical Solvers for FPGA Accelerators
  2nd International Workshop on High-Performance Stencil Computations (HiStencils) (Amsterdam, 20. January 2015 - 20. January 2015)
  In: Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils) 2015
  URL: https://www12.cs.fau.de/downloads/schmittch/publications/SSHTKK15histencils.pdf
  BibTeX: Download
• Sousa É., Hannig F., Teich J.:
  Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
  International Embedded Systems Symposium (IESS) (Foz do Iguaçu, 3. November 2015 - 6. November 2015)
  In: Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, and Achim Rettberg (ed.): Proceedings of the International Embedded Systems Symposium (IESS) 2015
  DOI: 10.1007/978-3-319-90023-0
  URL: http://www.springer.com/us/book/9783319900223
  BibTeX: Download
• Sousa É., Hannig F., Teich J., Schlichtmann U., Chen Q.:
  Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
  18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015 (St. Goar, 1. June 2015 - 3. June 2015)
  In: In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2015
  DOI: 10.1145/2764967.2771933
  BibTeX: Download
• Tanase AP., Witterauf M., Hannig F., Teich J.:
  Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays
  ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015 (Austin, 21. September 2015 - 23. September 2015)
  In: Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2015
  DOI: 10.1109/MEMCOD.2015.7340486
  BibTeX: Download
• Tanase AP., Witterauf M., Teich J., Hannig F., Lari V.:
  On-demand fault-tolerant loop processing on massively parallel processor arrays
  26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 (Toronto, 27. July 2015 - 29. July 2015)
  In: In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
  DOI: 10.1109/ASAP.2015.7245734
  BibTeX: Download
• Teich J., Boppu S., Hannig F., Lari V.:
  Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays
  In: Luk, Wayne, Constantinides, George A. (ed.): Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung, 2015, p. 167-206
  ISBN: 978-1-78326-696-8
  DOI: 10.1142/9781783266975_0010
  BibTeX: Download
• Witterauf M., Tanase AP., Hannig F., Teich J.:
  Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing
  11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 12. July 2015 - 18. July 2015)
  In: Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) 2015
  BibTeX: Download

2014

• Boppu S., Hannig F., Teich J.:
  Compact Code Generation for Tightly-Coupled Processor Arrays
  In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 77(1-2) (2014), p. 5-29
  ISSN: 1387-5485
  DOI: 10.1007/s11265-014-0891-2
  BibTeX: Download
• Gangadharan D., Tanase AP., Hannig F., Teich J.:
  Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays
  DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES) (Dresden, Germany, 28. March 2014 - 28. March 2014)
  URL: https://ecsi.org/resource/workshop/2014/3PMCES/DATE/paper/timing-analysis-heterogeneous-architecture-massively-parallel-processor-arrays
  BibTeX: Download
• Grebhahn A., Kuckuk S., Schmitt C., Köstler H., Siegmund N., Apel S., Hannig F., Teich J.:
  Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror
  In: Parallel Processing Letters 24 (2014)
  ISSN: 0129-6264
  DOI: 10.1142/S0129626414410011
  BibTeX: Download
• Hannig F., Koch D., Ziener D. (ed.):
  Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
  2014
  BibTeX: Download
• Hannig F., Lari V., Boppu S., Tanase AP., Reiche O.:
  Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach
  In: ACM Transactions on Embedded Computing Systems 13 (2014), p. 133:1-133:29
  ISSN: 1539-9087
  DOI: 10.1145/2584660
  BibTeX: Download
• Hannig F., Teich J. (ed.):
  Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014)
  2014
  BibTeX: Download
• Kuckuk S., Schmitt C., Köstler H., Hannig F., Teich J.:
  Generating Highly Parallel Geometric Multigrid Solvers with the ExaStencils Apporach
  3rd Workshop on Extreme-scale Programming Tools (New Orleans, 17. November 2014 - 17. November 2014)
  BibTeX: Download
• Lari V., Tanase AP., Hannig F., Teich J.:
  Massively Parallel Processor Architectures for Resource-aware Computing
  First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing ) (Paderborn, 29. May 2014 - 30. May 2014)
  In: Proc. of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) 2014
  BibTeX: Download
• Lengauer C., Apel S., Bolten M., Größlinger A., Hannig F., Köstler H., Rüde U., Teich J., Grebhahn A., Kronawitter S., Kuckuk S., Rittich H., Schmitt C.:
  ExaStencils: Advanced Stencil-Code Engineering - First Project Report
  (2014)
  Open Access: http://www.fim.uni-passau.de/fileadmin/files/forschung/mip-berichte/MIP1401.pdf
  BibTeX: Download
  (Techreport)
• Lengauer C., Apel S., Größlinger A., Grebhahn A., Kronawitter S., Bolten M., Rittich H., Hannig F., Köstler H., Rüde U., Teich J., Kuckuk S., Schmitt C.:
  ExaStencils: Advanced Stencil-Code Engineering
  Euro-Par: Parallel Processing Workshops (Porto, 25. August 2014 - 26. August 2014)
  In: Proceedings of Euro-Par 2014: Parallel Processing Workshops, Berlin; Heidelberg: 2014
  DOI: 10.1007/978-3-319-14313-2_47
  URL: http://link.springer.com/content/pdf/10.1007/978-3-319-14313-2_47.pdf
  BibTeX: Download
• Membarth R., Reiche O., Hannig F., Teich J.:
  Code Generation for Embedded Heterogeneous Architectures on Android
  Conference on Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. March 2014)
  In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2014
  DOI: 10.7873/DATE2014.099
  BibTeX: Download
• Membarth R., Reiche O., Schmitt C., Hannig F., Teich J., Stürmer M., Köstler H.:
  Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language
  In: Journal of Parallel and Distributed Computing 74 (2014), p. 3191-3201
  ISSN: 0743-7315
  DOI: 10.1016/j.jpdc.2014.08.008
  BibTeX: Download
• Paul J., Stechele W., Sousa É., Lari V., Hannig F., Teich J., Kröhnert M., Asfour T.:
  Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
  2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 (Madrid, 8. October 2014 - 10. October 2014)
  In: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Gières, France: 2014
  DOI: 10.1109/DASIP.2014.7115616
  BibTeX: Download
• Reiche O., Schmid M., Hannig F., Membarth R., Teich J.:
  Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators
  International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (New Dehli, 12. October 2014 - 17. October 2014)
  In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA: 2014
  DOI: 10.1145/2656075.2656081
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Towards Actor-oriented Programming on PGAS-based Multicore Architectures
  First International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (Lübeck)
  In: Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) 2014
  BibTeX: Download
• Schmid M., Apelt N., Hannig F., Teich J.:
  An Image Processing Library for C-based High-Level Synthesis
  Field-Programmable Logic and Applications (FPL) (Munich, 1. September 2014 - 5. September 2014)
  In: Proc. of Field-Programmable Logic and Applications (FPL), New York, NY, USA: 2014
  DOI: 10.1109/FPL.2014.6927424
  BibTeX: Download
• Schmid M., Hannig F., Tanase AP., Teich J.:
  High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model
  In: Parallel Computing: Accelerating Computational Science and Engineering (CSE), Amsterdam, The Netherlands: IOS Press, 2014, p. 497-506 (Advances in Parallel Computing, Vol.25)
  ISBN: 978-1-61499-380-3
  DOI: 10.3233/978-1-61499-381-0-497
  BibTeX: Download
• Schmid M., Reiche O., Schmitt C., Hannig F., Teich J.:
  Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
  First International Workshop on FPGAs for Software Programmers (FSP) (Munich, 1. September 2014 - 1. September 2014)
  In: Proc. of the First International Workshop on FPGAs for Software Programmers (FSP) 2014
  URL: http://arxiv.org/abs/1408.4721
  BibTeX: Download
• Schmid M., Tanase AP., Hannig F., Teich J., Bhadouria VS., Ghoshal D.:
  Domain-Specific Augmentations for High-Level Synthesis
  25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Zurich, 18. June 2014 - 20. June 2014)
  In: Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, NY, USA: 2014
  DOI: 10.1109/ASAP.2014.6868653
  BibTeX: Download
• Schmitt C., Kuckuk S., Hannig F., Köstler H., Teich J.:
  ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers
  4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (New Orleans, LA, USA, 17. November 2014 - 17. November 2014)
  In: Proc. of the 4th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), New York, NY, USA: 2014
  DOI: 10.1109/WOLFHPC.2014.11
  BibTeX: Download
• Schmitt C., Kuckuk S., Köstler H., Hannig F., Teich J.:
  An Evaluation of Domain-Specific Language Technologies for Code Generation
  14th International Conference on Computational Science and its Applications (ICCSA) (Minho, Guimaraes, 30. June 2014 - 3. July 2014)
  In: Proc. of the 14th International Conference on Computational Science and its Applications (ICCSA), New York, NY, USA: 2014
  DOI: 10.1109/ICCSA.2014.16
  BibTeX: Download
• Sousa É., Gangadharan D., Hannig F., Teich J.:
  Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures
  17th Euromicro Conference on Digital System Design, DSD 2014 (Verona, 27. August 2014 - 29. August 2014)
  In: Proceedings of the EUROMICRO Digital System Design Conference (DSD) 2014
  DOI: 10.1109/DSD.2014.105
  BibTeX: Download
• Sousa É., Paul J., Lari V., Hannig F., Teich J., Stechele W.:
  Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture.
  Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) (Dresden, 24. March 2014 - 28. December 2017)
  In: Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE) 2014
  Open Access: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
  URL: https://www.date-conference.com/system/files/file/date14/ubooth/2615.pdf
  BibTeX: Download
• Tanase AP., Witterauf M., Teich J., Hannig F.:
  Symbolic inner loop parallelisation for massively parallel processor arrays
  12th ACM/IEEE International Conference on Methods and Models for System Design, MEMOCODE 2014 (Lausanne, 19. October 2014 - 21. October 2014)
  In: Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2014
  DOI: 10.1109/MEMCOD.2014.6961865
  BibTeX: Download
• Tate A., Kamil A., Dubey A., Größlinger A., Chamberlain B., Goglin B., Edwards CH., Newburn C., Padua D., Unat D., Jeannot E., Hannig F., Gysi T., Ltaief H., Sexton J., Labarta J., Shalf J., Fürlinger K., O’Brien K., Linardakis L., Besta M., Sawley MC., Abraham M., Bianco M., Pericàs M., Maruyama N., Kelly PHJ., Messmer P., Ross RB., Cledat R., Matsuoka S., Schulthess T., Hoefler T., Leung VJ.:
  White Paper: Programming Abstractions for Data Locality
  PADAL Workshop 2014 (Swiss National Supercomputing Center (CSCS), Lugano, Switzerland, 28. April 2014 - 29. April 2014)
  In: Proc. of PADAL Workshop 2014
  URL: http://www.padalworkshop.org/white-paper/
  BibTeX: Download
• Teich J., Tanase AP., Hannig F.:
  Symbolic Mapping of Loop Programs onto Processor Arrays
  In: Journal of Signal Processing Systems, Berlin; Heidelberg: Springer-Verlag, 2014, p. 31-59
  DOI: 10.1007/s11265-014-0905-0
  BibTeX: Download

2013

• Boppu S., Hannig F., Teich J.:
  Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators
  24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
  In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
  DOI: 10.1109/ASAP.2013.6567544
  BibTeX: Download
• Boppu S., Lari V., Hannig F., Teich J.:
  Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
  Synopsys Users Group Conference (SNUG) (Munich, 14. May 2013 - 14. May 2013)
  In: Proc. Synopsys Users Group Conference 2013
  BibTeX: Download
• Hannig F., Schmid M., Lari V., Boppu S., Teich J.:
  System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures
  ACM International Conference on Computing Frontiers (CF) (Ischia, 14. May 2013 - 16. May 2013)
  In: Proc. ACM International Conference on Computing Frontiers, New York, NY, USA: 2013
  DOI: 10.1145/2482767.2482770
  BibTeX: Download
• Roloff S., Weichslgartner A., Heißwolf J., Hannig F., Teich J.:
  NoC Simulation in Heterogeneous Architectures for PGAS Programming Model
  16th International Workshop on Software and Compilers for Embedded Systems (M-SCOPES) (St. Goar, 19. June 2013 - 21. June 2013)
  In: Proc. 16th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2013
  DOI: 10.1145/2463596.2463606
  BibTeX: Download
• Schmid M., Blocherer M., Hannig F., Teich J.:
  Real-Time Range Image Preprocessing on FPGAs
  International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, 9. December 2013 - 11. December 2013)
  In: Proc. International Conference on Reconfigurable Computing and FPGAs 2013
  DOI: 10.1109/ReConFig.2013.6732325
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
  In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
  BibTeX: Download
• Sousa É., Tanase AP., Hannig F., Teich J.:
  A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
  2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
  In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
  BibTeX: Download
• Sousa É., Tanase AP., Lari V., Hannig F., Teich J., Paul J., Stechele W., Kröhnert M., Asfour T.:
  Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
  25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
  In: Proc. 25th Workshop on Parallel Systems and Algorithms, Berlin, Germany: 2013
  BibTeX: Download
• Tanase AP., Lari V., Hannig F., Teich J.:
  Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing
  International Conference on Parallel Computing (ParCo) (Munich, 10. September 2013 - 13. September 2013)
  In: Proc. International Conference on Parallel Computing 2013
  BibTeX: Download
• Teich J., Tanase AP., Hannig F.:
  Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
  24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
  In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
  DOI: 10.1109/ASAP.2013.6567543
  BibTeX: Download

2012

• Gerndt M., Hannig F., Herkersdorf A., Hollmann A., Meyer M., Roloff S., Weidendorfer J., Wild T., Zaib A.:
  An Integrated Simulation Framework for Invasive Computing
  Forum on Specification & Design Languages (FDL) (Vienna, 18. September 2012 - 20. September 2012)
  In: Proc. of the Forum on Specification & Design Languages (FDL), New York, NY, USA: 2012
  BibTeX: Download
• Lari V., Muddasani S., Boppu S., Hannig F., Schmid M., Teich J.:
  Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays
  In: ACM Transactions on Design Automation of Electronic Systems 18 (2012), p. 1-25
  ISSN: 1084-4309
  DOI: 10.1145/2390191.2390193
  BibTeX: Download
• Lari V., Muddasani S., Boppu S., Hannig F., Teich J.:
  Design of low power on-chip processor arrays
  2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012 (Delft, 9. July 2012 - 11. July 2012)
  In: Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2012
  DOI: 10.1109/ASAP.2012.10
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging
  11th International Symposium on Parallel and Distributed Computing (ISPDC) (Munich, 25. June 2012 - 29. June 2012)
  In: Proc. of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), New York, NY, USA: 2012
  DOI: 10.1109/ISPDC.2012.36
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Generating Device-specific GPU Code for Local Operators in Medical Imaging
  26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) (Shanghai, 21. May 2012 - 25. May 2012)
  In: Proc. of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), New York, NY, USA: 2012
  DOI: 10.1109/IPDPS.2012.59
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Mastering Software Variant Explosion for GPU Accelerators
  In: Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), Berlin; Heidelberg: Springer, 2012, p. 123-132 (Lecture Notes on Computer Science (LNCS))
  DOI: 10.1007/978-3-642-36949-0_15
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Köstler H.:
  Towards Domain-specific Computing for Stencil Codes in HPC
  2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) (Salt Lake City, UT, 10. November 2012 - 16. November 2012)
  In: Proceedings of the 2nd International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC) 2012
  DOI: 10.1109/SC.Companion.2012.136
  BibTeX: Download
• Membarth R., Lupp JH., Hannig F., Teich J., Körner M., Eckert W.:
  Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging
  25th International Conference on Architecture of Computing Systems (ARCS) (Munich, 28. February 2012 - 2. March 2012)
  In: Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS), New York, NY, USA: 2012
  DOI: 10.1007/978-3-642-28293-5_13
  BibTeX: Download
• Muddasani S., Boppu S., Hannig F., Kuzmin B., Lari V., Teich J.:
  A Prototype of an Invasive Tightly-Coupled Processor Array
  2012 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Karlsruhe, 23. October 2012 - 25. October 2012)
  In: Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), New York, NY, USA: 2012
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs
  17th Asia and South Pacific Design Automation Conference (ASP-DAC) (Sydney, 30. January 2012 - 2. February 2012)
  In: Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), New York, NY, USA: 2012
  DOI: 10.1109/ASPDAC.2012.6164943
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation
  15th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Schloss Rheinfels, St. Goar, 15. May 2012 - 16. May 2012)
  In: Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), New York, NY, USA: 2012
  DOI: 10.1145/2236576.2236582
  BibTeX: Download
• Roloff S., Hannig F., Teich J.:
  Simulation of Resource-Aware Applications on Heterogeneous Architectures
  8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. July 2012 - 14. July 2012)
  In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
  BibTeX: Download
• Schmid M., Hannig F., Teich J.:
  Power Management Strategies for Serial RapidIO Endpoints in FPGAs
  IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM) (Toronto, 29. April 2012 - 1. May 2012)
  In: Proc. of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), New York, NY, USA: 2012
  DOI: 10.1109/FCCM.2012.26
  BibTeX: Download
• Tanase AP., Hannig F., Teich J.:
  Symbolic loop parallelization of static control programs
  8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (Fiuggi, 8. July 2012 - 14. July 2012)
  In: Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Ghent, Belgium: 2012
  BibTeX: Download

2011

• Boppu S., Hannig F., Teich J., Pérez-Andrade R.:
  Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays
  2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig'11) (Cancun, 30. November 2011 - 2. December 2011)
  In: Proc. of ReConFig, New York, NY, USA: 2011
  DOI: 10.1109/ReConFig.2011.91
  URL: http://www.computer.org/portal/web/csdl/doi/10.1109/ReConFig.2011.91
  BibTeX: Download
• Cavallaro JR., Ercegovac MD., Hannig F., Ienne P., Swartzlander Jr. EE., Tenca AF. (ed.):
  Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
  New York, NY, USA: 2011
  ISBN: 978-1-4577-1292-0
  BibTeX: Download
• Hannig F., Roloff S., Snelting G., Teich J., Zwinkau A.:
  Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10
  14th International Workshop on Software and Compilers for Embedded Systems (St. Goar, 27. June 2011 - 28. June 2011)
  In: Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, New York, NY, USA: 2011
  DOI: 10.1145/1988932.1988941
  BibTeX: Download
• Kissler D., Gran D., Salcic Z., Hannig F., Teich J.:
  Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays
  In: IEEE Embedded Systems Letters 3 (2011), p. 58-61
  ISSN: 1943-0663
  DOI: 10.1109/LES.2011.2124438
  BibTeX: Download
• Kissler D., Hannig F., Teich J.:
  Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays
  In: Journal of Low Power Electronics 7 (2011), p. 29-40
  ISSN: 1546-1998
  DOI: 10.1166/jolpe.2011.1114
  BibTeX: Download
• Kouveli G., Hannig F., Lupp JH., Teich J.:
  Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor
  3rd Many-core Applications Research Community (MARC) Symposium (Ettlingen, 5. July 2011 - 6. July 2011)
  In: Proceedings of the 3rd MARC Symposium, Karlsruhe, Germany: 2011
  DOI: 10.5445/KSP/1000023937
  BibTeX: Download
• Lari V., Hannig F., Teich J.:
  Distributed Resource Reservation in Massively Parallel Processor Arrays
  25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS'11) (Anchorage, AK, 16. May 2011 - 20. May 2011)
  In: Proc. of the 25th IEEE International Symposium on Parallel and Distributed Processing, New York, NY, USA: 2011
  DOI: 10.1109/IPDPS.2011.157
  BibTeX: Download
• Lari V., Narovlyanskyy A., Hannig F., Teich J.:
  Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays
  22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'11) (Santa Monica, CA, 11. September 2011 - 14. September 2011)
  In: Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, New York, NY, USA: 2011
  DOI: 10.1109/ASAP.2011.6043240
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration
  9th IEEE Symposium on Application Specific Processors (SASP) (San Diego, CA, USA, 5. June 2011 - 6. June 2011)
  In: Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP) 2011
  DOI: 10.1109/SASP.2011.5941083
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration
  24th International Conference on Architecture of Computing Systems (ARCS) (Lake Como, 24. February 2011 - 25. February 2011)
  In: Proceedings of the 24th International Conference on Architecture of Computing Systems (ARCS), Heidelberg: 2011
  DOI: 10.1007/978-3-642-19137-4_6
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Litz G., Hornegger H.:
  Detector Defect Correction of Medical Images on Graphics Processors
  SPIE: Medical Imaging : Image Processing (Lake Buena Vista, Orlando, FL, 14. February 2011 - 16. February 2011)
  In: Proceedings of the SPIE: Medical Imaging 2011: Image Processing 2011
  DOI: 10.1117/12.877656
  BibTeX: Download

2010

• Charot F., Hannig F., Teich J., Wolinski C. (ed.):
  Proc. 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors
  New York, NY, USA: 2010
  ISBN: 978-1-4244-6967-3
  DOI: 10.1109/ASAP.2010.5540766
  BibTeX: Download
• Dutta H., Hannig F., Schmid M., Keinert J.:
  Modeling and synthesis of communication subsystems for loop accelerator pipelines
  21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. July 2010 - 9. July 2010)
  In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
  DOI: 10.1109/ASAP.2010.5540760
  BibTeX: Download
• Hannig F., Schmid M., Teich J., Hornegger H.:
  A Deeply Pipelined and Parallel Architecture for Denoising Medical Images
  IEEE International Conference on Field Programmable Technology (FPT'10) (Beijing, 8. December 2010 - 10. December 2010)
  In: Proc. IEEE International Conference on Field Programmable Technology 2010
  DOI: 10.1109/FPT.2010.5681464
  BibTeX: Download
• Membarth R., Hannig F., Teich J., Körner M., Eckert W.:
  Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures
  Embedded World Conference (Nuremberg, 3. March 2010 - 5. March 2010)
  In: Proc. Embedded World Conference 2010
  BibTeX: Download
• Schmid M., Hannig F., Teich J., Diefenbach R., Pettendorf R., Hornegger H.:
  Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect
  Embedded World Conference (Nuremberg, 3. March 2010 - 5. March 2010)
  In: Proceedings of the Embedded World Conference 2010
  BibTeX: Download
• Vander Aa T., Raghavan P., Mahlke S., De Sutter B., Shrivastava A., Hannig F.:
  Compilation Techniques for CGRAs: Exploring All Parallelization Approaches
  International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'10) (Scottsdale, AZ, 24. October 2010 - 29. October 2010)
  In: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis 2010
  DOI: 10.1145/1878961.1878995
  BibTeX: Download

2009

• Arifin F., Amouri A., Hannig F., Teich J.:
  FPGA Implementation of an Invasive Computing Architecture
  IEEE International Conference on Field Programmable Technology (FPT) (Sydney, 9. December 2009 - 11. December 2009)
  In: Proceedings of the IEEE International Conference on Field Programmable Technology 2009
  DOI: 10.1109/FPT.2009.5377633
  BibTeX: Download
• Arifin F., Membarth R., Amouri A., Hannig F., Teich J.:
  FSM-Controlled Architectures for Linear Invasion
  17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (Florianópolis)
  In: Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration 2009
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis
  22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
  In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
  DOI: 10.1007/978-3-642-00454-4_23
  BibTeX: Download
• Dutta H., Kissler D., Hannig F., Kupriyanov O., Teich J., Pottier B.:
  A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors
  In: Microprocessors and Microsystems 33 (2009), p. 53-62
  ISSN: 0141-9331
  DOI: 10.1016/j.micpro.2008.08.007
  BibTeX: Download
• Dutta H., Zhai J., Hannig F., Teich J.:
  Impact of loop tiling on the controller logic of acceleration engines
  2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009 (Boston, MA, 7. July 2009 - 9. July 2009)
  In: Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2009
  DOI: 10.1109/ASAP.2009.21
  BibTeX: Download
• Dutta H., Zhai J., Hannig F., Teich J.:
  Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines
  20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Boston, MA, 7. July 2009 - 9. July 2009)
  In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors 2009
  BibTeX: Download
• Hannig F.:
  Scheduling Techniques for High-Throughput Loop Accelerators (Dissertation, 2009)
  BibTeX: Download
• Hannig F., Dutta H., Teich J.:
  Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning
  22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
  In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
  DOI: 10.1007/978-3-642-00454-4_5
  BibTeX: Download
• Keinert J., Dutta H., Hannig F., Haubelt C., Teich J.:
  Model-based synthesis and optimization of static multi-rate image processing algorithms
  2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (Nice, 20. April 2009 - 24. April 2009)
  In: Proceedings of Design, Automation and Test in Europe (DATE 2009) 2009
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=70350072695&origin=inward
  BibTeX: Download
• Kissler D., Strawetz A., Hannig F., Teich J.:
  Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures
  In: Journal of Low Power Electronics 5 (2009), p. 96-105
  ISSN: 1546-1998
  DOI: 10.1166/jolpe.2009.1008
  BibTeX: Download
• Lari V., Hannig F., Teich J.:
  System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance
  4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC) (Vienna, 22. September 2009 - 25. September 2009)
  In: Proceedings of the 4th International Symposium on Embedded Multicore Systems-on-Chip 2009
  DOI: 10.1109/ICPPW.2009.72
  BibTeX: Download
• Membarth R., Hannig F., Dutta H., Teich J.:
  Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
  9th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop) (Island of Samos, 20. July 2009 - 23. July 2009)
  In: Proceedings of the 9th International Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS), Berlin / Heidelberg: 2009
  DOI: 10.1007/978-3-642-03138-0_31
  BibTeX: Download
• Membarth R., Hannig F., Dutta H., Teich J.:
  Optimization Flow for Algorithm Mapping on Graphics Cards
  Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) (Barcelona, 12. July 2009 - 18. July 2009)
  In: Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems 2009
  BibTeX: Download
• Membarth R., Kutzer P., Dutta H., Hannig F., Teich J.:
  Acceleration of multiresolution imaging algorithms: A comparative study
  2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009 (Boston, MA, 7. July 2009 - 9. July 2009)
  In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2009
  DOI: 10.1109/ASAP.2009.8
  BibTeX: Download

2008

• Dutta Hritam, Hannig Frank, Hartl Matthias, Kissler Dmitrij, Teich Jürgen:
  Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends
  Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe (Munich, Germany)
  In: Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe, New York: 2008
  BibTeX: Download
• Dutta H., Hannig F., Ruckdeschel H., Teich J.:
  Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices
  2nd HiPEAC Workshop on Reconfigurable Computing (Gothenburg)
  In: Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing 2008
  BibTeX: Download
• Hannig F., Ruckdeschel H., Dutta H., Teich J.:
  PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
  Fourth International Workshop on Applied Reconfigurable Computing (ARC) (London, 26. March 2008 - 28. March 2008)
  In: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, Berlin Heidelberg: 2008
  DOI: 10.1007/978-3-540-78610-8_30
  BibTeX: Download
• Hannig F., Ruckdeschel H., Teich J.:
  The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications
  GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Freiburg, 3. March 2008 - 5. March 2008)
  In: Proceedings of the GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2008
  BibTeX: Download
• Kissler D., Strawetz A., Hannig F., Teich J.:
  Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
  18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (Lisbon, 10. September 2008 - 12. September 2008)
  In: Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2008
  BibTeX: Download
• Kupriyanov O., Hannig F., Kissler D., Teich J.:
  MAML: An ADL for Designing Single and Multiprocessor Architectures
  In: Prabhat Mishra and Nikil Dutt (ed.): Processor Description Languages, Elsevier Inc., 2008, p. 295-327 (Systems on Silicon Series)
  ISBN: 9780123742872
  DOI: 10.1016/B978-012374287-2.50015-X
  BibTeX: Download
• Schaffer R., Merker R., Hannig F., Teich J.:
  Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
  11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
  In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
  DOI: 10.1109/DSD.2008.24
  BibTeX: Download
• Wolinski C., Kuchcinski K., Teich J., Hannig F.:
  Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures
  International Conference on Field Programmable Logic and Applications (FPL) (Heidelberg, 8. September 2008 - 10. September 2008)
  In: Proceedings of the International Conference on Field Programmable Logic and Applications, New York: 2008
  DOI: 10.1109/FPL.2008.4629969
  BibTeX: Download
• Wolinski C., Kuchcinski K., Teich J., Hannig F.:
  Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
  11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
  In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
  DOI: 10.1109/DSD.2008.1
  BibTeX: Download
• Wolinski C., Kuchcinski K., Teich J., Hannig F.:
  Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
  16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (Palo Alto, CA, 14. April 2008 - 15. April 2008)
  In: Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines 2008
  DOI: 10.1109/FCCM.2008.16
  BibTeX: Download

2007

• Dutta H., Hannig F., Kupriyanov O., Kissler D., Teich J., Schaffer R., Siegel S., Merker R., Pottier B.:
  Massively Parallel Processor Architectures: A Co-design Approach
  3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) (Montpellier, 18. June 2007 - 20. June 2007)
  In: Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) 2007
  BibTeX: Download
• Dutta H., Hannig F., Ruckdeschel H., Teich J.:
  Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays
  In: Journal of Systems Architecture 53 (2007), p. 300-309
  ISSN: 1383-7621
  DOI: 10.1016/j.sysarc.2006.10.009
  BibTeX: Download
• Kissler D., Hannig F., Teich J.:
  Schwach-programmiert macht stark
  In: Design & Elektronik (2007), p. 34-39
  ISSN: 0933-8667
  BibTeX: Download
• Kupriyanov O., Hannig F., Kissler D., Teich J., Lallet J., Sentieys O., Pillement S.:
  Modeling of interconnection networks in massively parallel processor architectures
  20th International Conference on Architecture of Computing Systems, ARCS 2007 (Zurich, 12. March 2007 - 15. March 2007)
  In: Proceedings of the 20th International Conference on Architecture of Computing Systems (ARCS 2007) 2007
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=37249015485&origin=inward
  BibTeX: Download
• Kupriyanov O., Kissler D., Hannig F., Teich J.:
  Efficient event-driven simulation of parallel processor architectures
  10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007 (Nice)
  In: Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2007
  DOI: 10.1145/1269843.1269854
  BibTeX: Download
• Teich J., Hannig F., Ruckdeschel H., Dutta H., Kissler D., Stravet A.:
  A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation
  International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, 25. June 2007 - 28. June 2007)
  In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 2007
  BibTeX: Download

2006

• Dutta H., Hannig F., Heigl B., Hornegger H., Teich J.:
  A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
  IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Steamboat Springs, CO, 11. September 2006 - 13. September 2006)
  In: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors 2006
  DOI: 10.1109/ASAP.2006.4
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms
  In: Technical Report 04-2006, 2006
  BibTeX: Download
  (Techreport)
• Dutta H., Hannig F., Teich J.:
  Controller Synthesis for Mapping Partitioned Programs on Array Architectures
  19th International Conference on Architecture of Computing Systems (ARCS) (Frankfurt am Main, 13. March 2006 - 16. March 2006)
  In: Proceedings of the 19th International Conference on Architecture of Computing Systems, Berlin, Heidelberg, New York: 2006
  DOI: 10.1007/11682127_13
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  Hierarchical Partitioning for Piecewise Linear Algorithms
  5th International Conference on Parallel Computing in Electrical Engineering (PARELEC) (Bialystok, 13. September 2006 - 17. September 2006)
  In: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering 2006
  DOI: 10.1109/PARELEC.2006.43
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology
  In: International Journal of Embedded Systems 2 (2006), p. 114-127
  ISSN: 1741-1068
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints
  6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing (Paderborn, 17. January 2006 - 18. January 2006)
  In: Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, Paderborn, Germany: 2006
  BibTeX: Download
• Hannig F., Dutta H., Teich J.:
  Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays -- Architectural Parameters and Methodology
  In: International Journal of Embedded Systems 2 (2006), p. 114-127
  ISSN: 1741-1068
  DOI: 10.1504/IJES.2006.010170
  BibTeX: Download
• Hannig F., Merker R., Siegel S., Teich J.:
  Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays
  18th International Conference on Parallel and Distributed Computing and Systems (PDCS) (Dallas, TX, 13. November 2006 - 15. November 2006)
  In: Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems 2006
  BibTeX: Download
• Kissler D., Hannig F., Kupriyanov O., Teich J.:
  A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template
  2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) (, 3. July 2006 - 5. July 2006)
  In: Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) 2006
  BibTeX: Download
• Kissler D., Hannig F., Kupriyanov O., Teich J.:
  Hardware cost analysis for weakly programmable processor arrays
  2006 International Symposium on System-on-Chip, SOC (Tampere, 14. November 2006 - 16. November 2006)
  In: Proceedings of the International Symposium on System-on-Chip (SoC) 2006
  DOI: 10.1109/ISSOC.2006.321996
  BibTeX: Download
• Kissler D., Kupriyanov O., Hannig F., Koch D., Teich J.:
  A Generic Framework for Rapid Prototyping of System-on-Chip Designs
  International Conference on Computer Design (CDES) (Las Vegas, NV)
  In: Proceedings of the International Conference on Computer Design (CDES) 2006
  BibTeX: Download
• Kissler D., Kupriyanov O., Hannig F., Teich J.:
  A highly parameterizable parallel processor array architecture
  2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (Bangkok, 13. December 2006 - 15. December 2006)
  In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006) 2006
  DOI: 10.1109/FPT.2006.270293
  BibTeX: Download
• Kupriyanov O., Hannig F., Kissler D., Schaffer R., Teich J.:
  MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I
  In: Technical Report 03-2006, 2006
  BibTeX: Download
  (Techreport)
• Kupriyanov O., Hannig F., Kissler D., Teich J., Lallet J., Sentieys O., Pillement S.:
  Modeling of Interconnection Networks in Massively Parallel Processor Architectures
  In: Technical Report 05-2006, 2006
  BibTeX: Download
  (Techreport)
• Kupriyanov O., Hannig F., Kissler D., Teich J., Schaffer R., Merker R.:
  An Architecture Description Language for Massively Parallel Processor Architectures
  9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Dresden, 20. February 2006 - 22. February 2006)
  In: Proceedings of the 9th ITG/GMM/GI Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2006
  BibTeX: Download

2005

• Ahmadinia A., Bobda C., Fekete SP., Hannig F., Majer M., Teich J., Van Der Veen JC.:
  Defragmenting the Module Layout of a Partially Reconfigurable Device
  International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. June 2005 - 30. June 2005)
  In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
  BibTeX: Download
• Dutta H., Hannig F., Kupriyanov O., Teich J., Schaffer R., Siegel S., Merker R., Keryell R., Pottier B., Chillet D., Ménard D., Sentieys O.:
  Co-Design of Massively Parallel Embedded Processor Architectures
  First ReCoSoC Workshop (Montpellier)
  In: Proceedings of the first ReCoSoC Workshop 2005
  BibTeX: Download
• Dutta Hritam, Hannig Frank, Ruckdeschel Holger, Teich Jürgen:
  Automatic FIR Filter Generation for FPGAs
  Embedded Computer Systems: Architectures, Modeling, and Simulation. (Island of Samos, 18. July 2005 - 20. July 2005)
  In: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), Berlin, Heidelberg, New York: 2005
  BibTeX: Download
• Dutta H., Hannig F., Teich J.:
  Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures
  In: Technical Report 03-2005, 2005
  BibTeX: Download
  (Techreport)
• Hannig F., Teich J.:
  Output Serialization for FPGA-based and Coarse-grained Processor Arrays
  International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. June 2005 - 30. June 2005)
  In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
  BibTeX: Download
• Schlichter T., Hannig F., Haubelt C., Teich J.:
  Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems
  IEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005 (Samos)
  In: Proceedings of Application-specific Systems, Architectures and Processors (ASAP) 2005
  DOI: 10.1109/ASAP.2005.64
  BibTeX: Download

2004

• Hannig F., Dutta H., Teich J.:
  Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology
  18th International Parallel and Distributed Processing Symposium (IPDPS 2004), (Santa Fe, NM, 26. April 2004 - 30. April 2004)
  In: Proceedings of the 18th International Parallel and Distributed Processing Symposium 2004
  BibTeX: Download
• Hannig F., Dutta H., Teich J.:
  Regular Mapping for Coarse-grained Reconfigurable Architectures
  IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ) (Montreal, Quebec, 17. May 2004 - 21. May 2004)
  In: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing 2004
  BibTeX: Download
• Hannig F., Kupriyanov O., Teich J.:
  Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
  Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) (Washington, DC)
  In: Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) 2004
  BibTeX: Download
• Hannig F., Teich J.:
  Dynamic Piecewise Linear/Regular Algorithms
  Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ) (Dresden, 7. September 2004 - 10. September 2004)
  In: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) 2004
  BibTeX: Download
• Hannig F., Teich J.:
  Energy Estimation and Optimization for Piecewise Regular Processor Arrays
  In: Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, New York, U.S.A.,: Marcel Dekker, 2004, p. 107-126 (Signal Processing and Communication)
  ISBN: 0-8247-4711-9
  BibTeX: Download
• Hannig F., Teich J.:
  Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
  15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP ) (Galveston, TX, 27. September 2004 - 29. September 2004)
  In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2004) 2004
  BibTeX: Download
• Hannig F., Teich J.:
  Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms
  In: Technical Report 01-2004, 2004
  BibTeX: Download
  (Techreport)
• Kupriyanov O., Hannig F., Teich J.:
  High-speed event-driven RTL compiled simulation
  International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04) (Samos, 19. July 2004 - 21. July 2004)
  In: Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04) 2004
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=35048851603&origin=inward
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2002

• Hannig F., Teich J.:
  Energy Estimation for Piecewise Regular Processor Arrays
  Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), (Island of Samos, 22. July 2002 - 25. July 2002)
  In: Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation 2002
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• Hannig F., Teich J.:
  Energy Estimation of Nested Loop Programs
  14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), (Winnipeg, Manitoba, 10. August 2002 - 13. August 2002)
  In: Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures 2002
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• Hannig F., Teich J., Bednara M.:
  Generation of Distributed Loop Control
  In: E. Deprettere, J. Teich, and S. Vassiliadis (ed.): Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), Berlin, Germany: Springer, 2002, p. 154-170
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2001

• Bednara M., Hannig F., Teich J.:
  Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays
  35th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA)
  In: Matthews M.B. (ed.): Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers 2001
  URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0035573058&origin=inward
  BibTeX: Download
• Hannig F., Teich J.:
  Design Space Exploration for Massively Parallel Processor Arrays
  Sixth International Conference on Parallel Computing Technologies (PaCT-2001) (Novosibirsk, 3. September 2001 - 7. September 2001)
  In: Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001) 2001
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