Kategorie: SYSC

16JAN 2026
News
Best Paper Award
Pierre-Louis Sixdenier, Mark Deutel and Prof. Dr.-Ing. Jürgen Teich received the Best Paper Award at this year’s 18th IEEE International Symposium on Embedded Multicore/Many-Core Systems-On-Chip (MCSOC 2025). The award was given for their paper “Early-Exit Neural Architecture Search for Energy-Harvesting Edge Computing.” The award was presented during the event (December 15-18, 2025) in Singapore. In […]Pierre-Louis Sixdenier, Mark Deutel and Prof. Dr.-Ing. Jürgen Teich received the Best Paper Award at this year’s 18th IEEE International Symposium on Embedded Multicore/Many-Core Systems-On-Chip (MCSOC 2025). The award was given for their paper “Early-Exit Neural Architecture Search for Energy-Harvesting Edge Computing.” The award was presented during the event (December 15-18, 2025) in Singapore. In […]
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17OCT 2025
News
Embedded Talk “Deep Learning on Narrow Resources”
On Friday, October 10, 2025, the 19th Embedded Talk of the FAU Research Center ESI on the topic of “Deep Learning on Narrow Resources” took place at Friedrich-Alexander University Erlangen-Nuremberg. The event, which was attended by around 60 participants, provided a platform for experts and researchers from the industry to discuss current developments and challenges […]
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15OCT 2025
News
Sept. 30 – Oct. 3, 2025: Chair of Hardware/Software Co-Design visits Kyoto University and RIKEN, Japan
A delegation from the Chair of Hardware-Software Co-Design at FAU, led by Prof. Jürgen Teich, accepted an invitation from the Integrated Systems Engineering Laboratory (Prof. Takashi Sato, Prof. Kiichi Niitsu, Prof. Hiromitsu Awano) to visit Kyoto University in Japan. During a three-day workshop, the latest research results in the field of electronic design automation (EDA) […]
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22JUL 2025
News
22.07.2025: NHR PerfLab Seminar Talk by Prof. Teich
Prof. Teich gave a talk at the NHR PerfLab Seminar with the title “(Re-)Configurable Processor Arrays On-Chip—Low Energy/High Performance Loop Nest Acceleration”. Speaker: Prof. Dr. Jürgen Teich, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Date and time: Tuesday, July 22, 2025, 2:00 p.m. CEST Place: RRZE Seminar Room 2.049 or Zoom: https://go-nhr.de/perflab-seminar Please find all […]Prof. Teich gave a talk at the NHR PerfLab Seminar with the title “(Re-)Configurable Processor Arrays On-Chip—Low Energy/High Performance Loop Nest Acceleration”. Speaker: Prof. Dr. Jürgen Teich, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Date and time: Tuesday, July 22, 2025, 2:00 p.m. CEST Place: RRZE Seminar Room 2.049 or Zoom: https://go-nhr.de/perflab-seminar Please find all […]
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27MAY 2025
News
Promotion Jan Spieck, 16.5.2025
Jan Spieck successfully defended his doctoral thesis “A Learning-Based Methodology for Hybrid Application Mapping on Heterogeneous MPSoCs” on 16.5.25. Afterwards he received his doctoral hat.
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14MAY 2025
News
14.05.2025: Visit by Prof. Jie Han, University of Alberta
On May 15, Prof. Jie Han gave the following tutorial at our labs: Tutorial: Approximate Computing: Circuits, Systems and Applications Speaker: Prof. Dr. Jie Han, Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada Place: Seminar Room 1.150
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