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Verifikation digitaler Systeme

Language:

German

Short description:

Nowadays in industry there are as many verification engineers as design engineers needed. Nevertheless verification takes about 80% of the whole design time. Besides conventional verification processes like simulation, formal verification methods are used in modern designs. In contrast to simulation formal verification is based on exact mathematical methods to guarantee functional  system properties.

This lecture covers basic algorithms and concepts of modern tools for formal simulation-based verification of digital systems and the industrial use of such systems.

 

For more information please visit our german webpage