Invited Talk Prof. Aviral Shrivastava, 7 June 2023

Two men standing in front of windows
Prof. A. Shrivastava and Prof. J. Teich (from the right)

Prof. Aviral Shrivastava, from Arizona State University, gave his invited talk “An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” at the Department of Computer Science 12, on 7 June 2023.

Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. We propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE can identify the bottlenecks and therefore the reasons for design inefficiency and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.

Aviral Shrivastava is a full Professor in the School of Computing and Augmented Intelligence (SCAI) at the Arizona State University, where he established and heads the Make Programming Simple Lab ( He completed his Ph.D. in Information and Computer Science and from the University of California, Irvine, and bachelor’s in computer science and engineering from IIT Delhi.

The main theme of Prof. Shrivastava’s research in on making programming simple for embedded and cyber-physical systems. Prof. Shrivastava and his students have proposed novel computer architectures and compiler transformations for hardware error-tolerant computing, multicore computing, accelerated computing. They have also proposed languages, code generation and runtime for expressing and efficiently executing time-sensitive distributed intelligent applications.

Prof. Shrivastava has co-authored 1 book and has contributed chapters in 4 books. He has more than 120 articles and conference papers in top embedded system journals and conferences, like DAC, ESWEEK, ACM TECS, and ACM TCPS. His papers have received several awards, including nomination for best paper at DAC 2017, best student paper award at VLSI 2016, second highest ranked paper at LCTES 2010, and best paper candidate ASPDAC 2008. He published at least one paper every year at DAC (the top conference in the field) in the last decade (2011 to 2019). Overall, his works have received more than 3000 citations, growing at the rate of over 200 citations every year. His i50-index is 14, i10-index is 84, and h-index is 31 (reference Google Scholar). His inventions have been granted 5 patents, and 5 more applications are pending. Prof. Shrivastava is the recipient of the prestigious 2010 NSF CAREER award. His student’s theses were awarded CIDSE outstanding Ph.D. thesis award in 2021 and 2017 and outstanding master’s thesis awards in 2011 and 2014. Prof. Shrivastava’s research efforts have been supported by federal agencies (NSF, DOE, NIST), state funding agencies (SFAZ), as well as industry. His research portfolio is about $4M to date.

Prof. Shrivastava was the General Chair of 2022 Embedded Systems Week (ESWEEK), which is the top event in the field of Embedded Systems, comprising of several conferences, symposia, and workshops. He also serves in the Steering committee of the Languages Compilers, Theory, and tools for Embedded Systems (LCTES). Currently, he is the deputy Editor-in-Chief of IEEE Embedded Systems Letters (IEEE ESL), and associate editor for ACM Transactions of Cyber-Physical Systems (ACM TCPS), ACM Transactions Embedded Computing Systems (ACM TECS), and the IEEE Transactions on Computer Aided Design (IEEE TCAD). Previously he has served as the program chair of CODES+ISSS 2017 and 2018, LCTES 2019, and chair of the Design and Applications track of RTSS 2020.