PARO
Dedizierte massiv parallele Systeme
In diesem Projekt mit dem Namen PARO werden Verfahren zum Entwurf von feinkörnigen massiv parallelen VLSI Schaltungen untersucht. Eine Teilklasse dieser Architekturen ist unter dem Namen systolischer Felder bekannt. Obwohl diese Rechner keine eigenständigen Rechner darstellen, spielen sie - eingesetzt als Coprozessoren - eine wichtige Rolle in Systemen, die ein hohes Maß an Dediziertheit und Rechenleistung erfordern. Der Entwurf und die Integration dieser Komponenten in größere Systeme macht die Implementierung und Anwendung spezieller Entwurfsverfahren notwendig, die den Entwurf vom Algorithmus bis zur Schaltung automatisiert.
Mehr Details: https://cs12.cms.rrze.uni-erlangen.de/forschung/projekte/paro/paro-details
Publikationen
- Witterauf M., Tanase AP., Hannig F., Teich J.:
Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (London, 6. July 2016 - 8. July 2016)
In: Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016
BibTeX: Download - Hannig F.:
A Quick Tour of High-Level Synthesis Solutions for FPGAs
In: Dirk Koch, Frank Hannig, and Daniel Ziener (ed.): FPGAs for Software Programmers, Springer, 2016
DOI: 10.1007/978-3-319-26408-0_3
BibTeX: Download - Koch D., Hannig F., Ziener D. (ed.):
FPGAs for Software Programmers
Berlin; Heidelberg: 2016
ISBN: 978-3-319-26406-6
DOI: 10.1007/978-3-319-26408-0
BibTeX: Download - Tanase AP., Witterauf M., Sousa É., Lari V., Hannig F., Teich J.:
LoopInvader: A Compiler for Tightly Coupled Processor Arrays
Design, Automation and Test in Europe (DATE) (Dresden, 14. March 2016 - 18. March 2016)
In: Tool presentation at the University Booth 2016
URL: https://www.date-conference.com/system/files/file/date16/ubooth/37913.pdf
BibTeX: Download - Teich J., Lari V., Tanase AP., Witterauf M., Khosravi F., Meyer B.:
Techniques for on-demand structural redundancy for massively parallel processor arrays
In: Journal of Systems Architecture 61 (2015), p. 615-627
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2015.10.004
BibTeX: Download - Tanase AP., Witterauf M., Hannig F., Teich J.:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays
ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015 (Austin, 21. September 2015 - 23. September 2015)
In: Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2015
DOI: 10.1109/MEMCOD.2015.7340486
BibTeX: Download - Hannig F., Koch D., Ziener D. (ed.):
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)
2015
BibTeX: Download - Tanase AP., Witterauf M., Teich J., Hannig F., Lari V.:
On-demand fault-tolerant loop processing on massively parallel processor arrays
26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 (Toronto, 27. July 2015 - 29. July 2015)
In: In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2015
DOI: 10.1109/ASAP.2015.7245734
BibTeX: Download - Witterauf M., Tanase AP., Teich J., Lari V., Zwinkau A., Snelting G.:
Adaptive fault tolerance through invasive computing
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. June 2016 - 18. June 2015)
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
DOI: 10.1109/AHS.2015.7231155
BibTeX: Download - Lari V., Tanase AP., Teich J., Witterauf M., Khosravi F., Hannig F., Meyer B.:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays
NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015 (Montreal, 15. June 2016 - 18. June 2015)
In: Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems 2015
DOI: 10.1109/AHS.2015.7231157
BibTeX: Download - Tanase AP., Witterauf M., Teich J., Hannig F.:
Symbolic inner loop parallelisation for massively parallel processor arrays
12th ACM/IEEE International Conference on Methods and Models for System Design, MEMOCODE 2014 (Lausanne, 19. October 2014 - 21. October 2014)
In: Proceedings of the 12th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2014
DOI: 10.1109/MEMCOD.2014.6961865
BibTeX: Download - Teich J., Tanase AP., Hannig F.:
Symbolic Mapping of Loop Programs onto Processor Arrays
In: Journal of Signal Processing Systems, Berlin; Heidelberg: Springer-Verlag, 2014, p. 31-59
DOI: 10.1007/s11265-014-0905-0
BibTeX: Download - Hannig F., Lari V., Boppu S., Tanase AP., Reiche O.:
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach
In: ACM Transactions on Embedded Computing Systems 13 (2014), p. 133:1-133:29
ISSN: 1539-9087
DOI: 10.1145/2584660
BibTeX: Download - Schmid M., Hannig F., Tanase AP., Teich J.:
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model
In: Parallel Computing: Accelerating Computational Science and Engineering (CSE), Amsterdam, The Netherlands: IOS Press, 2014, p. 497-506 (Advances in Parallel Computing, Vol.25)
ISBN: 978-1-61499-380-3
DOI: 10.3233/978-1-61499-381-0-497
BibTeX: Download - Schmid M., Tanase AP., Hannig F., Teich J., Bhadouria VS., Ghoshal D.:
Domain-Specific Augmentations for High-Level Synthesis
25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (Zurich, 18. June 2014 - 20. June 2014)
In: Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, NY, USA: 2014
DOI: 10.1109/ASAP.2014.6868653
BibTeX: Download - Schmid M., Blocherer M., Hannig F., Teich J.:
Real-Time Range Image Preprocessing on FPGAs
International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Cancun, 9. December 2013 - 11. December 2013)
In: Proc. International Conference on Reconfigurable Computing and FPGAs 2013
DOI: 10.1109/ReConFig.2013.6732325
BibTeX: Download - Sousa É., Tanase AP., Hannig F., Teich J.:
A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
BibTeX: Download - Sousa É., Tanase AP., Hannig F., Teich J.:
Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays
2013 Conference on Design and Architectures for Signal and Image Processing (DASIP) (Cagliari, 8. October 2013 - 10. October 2013)
In: Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, New York, NY, USA: 2013
BibTeX: Download - Teich J., Tanase AP., Hannig F.:
Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567543
BibTeX: Download - Boppu S., Hannig F., Teich J.:
Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators
24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Washington, DC, 5. June 2013 - 7. June 2013)
In: Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors, New York, NY, USA: 2013
DOI: 10.1109/ASAP.2013.6567544
BibTeX: Download - Hannig F., Schmid M., Lari V., Boppu S., Teich J.:
System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures
ACM International Conference on Computing Frontiers (CF) (Ischia, 14. May 2013 - 16. May 2013)
In: Proc. ACM International Conference on Computing Frontiers, New York, NY, USA: 2013
DOI: 10.1145/2482767.2482770
BibTeX: Download - Sousa É., Tanase AP., Lari V., Hannig F., Teich J., Paul J., Stechele W., Kröhnert M., Asfour T.:
Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays
25th Workshop on Parallel Systems and Algorithms (PARS) (Erlangen)
In: Proc. 25th Workshop on Parallel Systems and Algorithms, Berlin, Germany: 2013
BibTeX: Download - Wasza J., Bauer S., Haase S., Schmid M., Reichert S., Hornegger J.:
RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing
VMV 2011: Vision, Modeling & Visualization (Berlin, 4. October 2011)
In: Eisert Peter, Hornegger Joachim, Polthier Konrad (ed.): VMV 2011: Vision, Modeling & Visualization 2011
DOI: 10.2312/PE/VMV/VMV11/057-064
URL: http://www5.informatik.uni-erlangen.de/Forschung/Publikationen/2011/Wasza11-RTR.pdf
BibTeX: Download - Cavallaro JR., Ercegovac MD., Hannig F., Ienne P., Swartzlander Jr. EE., Tenca AF. (ed.):
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
New York, NY, USA: 2011
ISBN: 978-1-4577-1292-0
BibTeX: Download - Teich J., Henkel J., Herkersdorf A., Schmitt-Landsiedel D., Schröder-Preikschat W., Snelting G.:
Invasive Computing: An Overview
In: M. Hübner and J. Becker (ed.): Multiprocessor System-on-Chip - Hardware Design and Tool Integration, New York: Springer, 2011, p. 241-268
ISBN: 978-1-4419-6459-5
DOI: 10.1007/978-1-4419-6460-1_11
URL: http://invasic.informatik.uni-erlangen.de/publications/invasic-overview.pdf
BibTeX: Download - Hannig F., Schmid M., Teich J., Hornegger H.:
A Deeply Pipelined and Parallel Architecture for Denoising Medical Images
IEEE International Conference on Field Programmable Technology (FPT'10) (Beijing, 8. December 2010 - 10. December 2010)
In: Proc. IEEE International Conference on Field Programmable Technology 2010
DOI: 10.1109/FPT.2010.5681464
BibTeX: Download - Vander Aa T., Raghavan P., Mahlke S., De Sutter B., Shrivastava A., Hannig F.:
Compilation Techniques for CGRAs: Exploring All Parallelization Approaches
International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'10) (Scottsdale, AZ, 24. October 2010 - 29. October 2010)
In: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis 2010
DOI: 10.1145/1878961.1878995
BibTeX: Download - Dutta H., Hannig F., Schmid M., Keinert J.:
Modeling and synthesis of communication subsystems for loop accelerator pipelines
21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. July 2010 - 9. July 2010)
In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
DOI: 10.1109/ASAP.2010.5540760
BibTeX: Download - Hannig F.:
Scheduling Techniques for High-Throughput Loop Accelerators (Dissertation, 2009)
BibTeX: Download - Dutta H., Zhai J., Hannig F., Teich J.:
Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines
20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Boston, MA, 7. July 2009 - 9. July 2009)
In: Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors 2009
BibTeX: Download - Keinert J., Dutta H., Hannig F., Haubelt C., Teich J.:
Model-based synthesis and optimization of static multi-rate image processing algorithms
2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (Nice, 20. April 2009 - 24. April 2009)
In: Proceedings of Design, Automation and Test in Europe (DATE 2009) 2009
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=70350072695&origin=inward
BibTeX: Download - Dutta H., Hannig F., Teich J.:
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_23
BibTeX: Download - Hannig F., Dutta H., Teich J.:
Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning
22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, 10. March 2009 - 13. March 2009)
In: Proceedings of the 22nd International Conference on Architecture of Computing Systems 2009
DOI: 10.1007/978-3-642-00454-4_5
BibTeX: Download - Dutta H., Kissler D., Hannig F., Kupriyanov O., Teich J., Pottier B.:
A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors
In: Microprocessors and Microsystems 33 (2009), p. 53-62
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2008.08.007
BibTeX: Download - Teich J.:
Invasive Algorithms and Architectures
In: it - Information Technology 50 (2008), p. 300-310
ISSN: 1611-2776
BibTeX: Download - Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures
International Conference on Field Programmable Logic and Applications (FPL) (Heidelberg, 8. September 2008 - 10. September 2008)
In: Proceedings of the International Conference on Field Programmable Logic and Applications, New York: 2008
DOI: 10.1109/FPL.2008.4629969
BibTeX: Download - Schaffer R., Merker R., Hannig F., Teich J.:
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.24
BibTeX: Download - Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
11th Euromicro Conference on Digital System Design (DSD) (Parma, 3. September 2008 - 5. September 2008)
In: Proceedings of the 11th Euromicro Conference on Digital System Design, New York: 2008
DOI: 10.1109/DSD.2008.1
BibTeX: Download - Wolinski C., Kuchcinski K., Teich J., Hannig F.:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (Palo Alto, CA, 14. April 2008 - 15. April 2008)
In: Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines 2008
DOI: 10.1109/FCCM.2008.16
BibTeX: Download - Hannig F., Ruckdeschel H., Dutta H., Teich J.:
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Fourth International Workshop on Applied Reconfigurable Computing (ARC) (London, 26. March 2008 - 28. March 2008)
In: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, Berlin Heidelberg: 2008
DOI: 10.1007/978-3-540-78610-8_30
BibTeX: Download - Hannig F., Ruckdeschel H., Teich J.:
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications
GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (Freiburg, 3. March 2008 - 5. March 2008)
In: Proceedings of the GI/ITG/GMM-Workshop -- Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen 2008
BibTeX: Download - Dutta H., Hannig F., Ruckdeschel H., Teich J.:
Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices
2nd HiPEAC Workshop on Reconfigurable Computing (Gothenburg)
In: Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing 2008
BibTeX: Download - Dutta H., Hannig F., Kupriyanov O., Kissler D., Teich J., Schaffer R., Siegel S., Merker R., Pottier B.:
Massively Parallel Processor Architectures: A Co-design Approach
3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) (Montpellier, 18. June 2007 - 20. June 2007)
In: Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC) 2007
BibTeX: Download - Teich J., Hannig F., Ruckdeschel H., Dutta H., Kissler D., Stravet A.:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, 25. June 2007 - 28. June 2007)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 2007
BibTeX: Download - Dutta H., Hannig F., Ruckdeschel H., Teich J.:
Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays
In: Journal of Systems Architecture 53 (2007), p. 300-309
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2006.10.009
BibTeX: Download - Hannig F., Merker R., Siegel S., Teich J.:
Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays
18th International Conference on Parallel and Distributed Computing and Systems (PDCS) (Dallas, TX, 13. November 2006 - 15. November 2006)
In: Proceedings of the 18th International Conference on Parallel and Distributed Computing and Systems 2006
BibTeX: Download - Dutta H., Hannig F., Teich J.:
Hierarchical Partitioning for Piecewise Linear Algorithms
5th International Conference on Parallel Computing in Electrical Engineering (PARELEC) (Bialystok, 13. September 2006 - 17. September 2006)
In: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering 2006
DOI: 10.1109/PARELEC.2006.43
BibTeX: Download - Dutta H., Hannig F., Teich J.:
A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms
In: Technical Report 04-2006, 2006
BibTeX: Download - Dutta H., Hannig F., Heigl B., Hornegger H., Teich J.:
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (Steamboat Springs, CO, 11. September 2006 - 13. September 2006)
In: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors 2006
DOI: 10.1109/ASAP.2006.4
BibTeX: Download - Dutta H., Hannig F., Teich J.:
Controller Synthesis for Mapping Partitioned Programs on Array Architectures
19th International Conference on Architecture of Computing Systems (ARCS) (Frankfurt am Main, 13. March 2006 - 16. March 2006)
In: Proceedings of the 19th International Conference on Architecture of Computing Systems, Berlin, Heidelberg, New York: 2006
DOI: 10.1007/11682127_13
BibTeX: Download - Dutta H., Hannig F., Teich J.:
Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints
6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing (Paderborn, 17. January 2006 - 18. January 2006)
In: Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, Paderborn, Germany: 2006
BibTeX: Download - Dutta H., Hannig F., Teich J.:
Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures
In: Technical Report 03-2005, 2005
BibTeX: Download - Dutta Hritam, Hannig Frank, Ruckdeschel Holger, Teich Jürgen:
Automatic FIR Filter Generation for FPGAs
Embedded Computer Systems: Architectures, Modeling, and Simulation. (Island of Samos, 18. July 2005 - 20. July 2005)
In: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), Berlin, Heidelberg, New York: 2005
BibTeX: Download - Hannig F., Teich J.:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA ) (Las Vegas, NV, 27. June 2005 - 30. June 2005)
In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms 2005
BibTeX: Download - Dutta H., Hannig F., Kupriyanov O., Teich J., Schaffer R., Siegel S., Merker R., Keryell R., Pottier B., Chillet D., Ménard D., Sentieys O.:
Co-Design of Massively Parallel Embedded Processor Architectures
First ReCoSoC Workshop (Montpellier)
In: Proceedings of the first ReCoSoC Workshop 2005
BibTeX: Download - Bednara M.:
Design Automation for Massively Parallel Processor Arrays: Transforming Regular Algorithms to Reconfigurable Hardware (Dissertation, 2004)
BibTeX: Download - Hannig F., Teich J.:
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms
In: Technical Report 01-2004, 2004
BibTeX: Download - Hannig F., Teich J.:
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP ) (Galveston, TX, 27. September 2004 - 29. September 2004)
In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2004) 2004
BibTeX: Download - Hannig F., Kupriyanov O., Teich J.:
Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) (Washington, DC)
In: Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES 2004) 2004
BibTeX: Download - Hannig F., Teich J.:
Dynamic Piecewise Linear/Regular Algorithms
Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC ) (Dresden, 7. September 2004 - 10. September 2004)
In: Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004) 2004
BibTeX: Download - Kupriyanov O., Hannig F., Teich J.:
High-speed event-driven RTL compiled simulation
International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04) (Samos, 19. July 2004 - 21. July 2004)
In: Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04) 2004
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=35048851603&origin=inward
BibTeX: Download - Hannig F., Dutta H., Teich J.:
Regular Mapping for Coarse-grained Reconfigurable Architectures
IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ) (Montreal, Quebec, 17. May 2004 - 21. May 2004)
In: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing 2004
BibTeX: Download - Hannig F., Dutta H., Teich J.:
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology
18th International Parallel and Distributed Processing Symposium (IPDPS 2004), (Santa Fe, NM, 26. April 2004 - 30. April 2004)
In: Proceedings of the 18th International Parallel and Distributed Processing Symposium 2004
BibTeX: Download - Hannig F., Teich J.:
Energy Estimation and Optimization for Piecewise Regular Processor Arrays
In: Chapter 6 in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, New York, U.S.A.,: Marcel Dekker, 2004, p. 107-126 (Signal Processing and Communication)
ISBN: 0-8247-4711-9
BibTeX: Download - Hannig F., Teich J.:
Energy Estimation of Nested Loop Programs
14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), (Winnipeg, Manitoba, 10. August 2002 - 13. August 2002)
In: Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures 2002
BibTeX: Download - Hannig F., Teich J.:
Energy Estimation for Piecewise Regular Processor Arrays
Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), (Island of Samos, 22. July 2002 - 25. July 2002)
In: Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation 2002
BibTeX: Download - Bednara M., Teich J.:
Interface Synthesis for FPGA Based VLSI Processor Arrays
The International Conference on Engineering of Reconfigurable Sytsems and Algorithms (ERSA02), (Las Vegas, Nevada, 24. June 2002 - 27. June 2002)
In: Proc. of The International Conference on Engineering of Reconfigurable Sytsems and Algorithms 2002
BibTeX: Download - Teich J., Thiele L.:
Exact Partitioning of Affine Dependence Algorithms
In: Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), Berlin, Germany: Springer, 2002, p. 135-151
BibTeX: Download - Teich J.:
Exact Partitioning of Affine Dependence Algorithms
SAMOS - Systems, Architectures, Modeling and Simulation Workshop, (Island of Samos)
In: Proc. SAMOS - Systems, Architectures, Modeling and Simulation Workshop 2001
BibTeX: Download - Hannig F., Teich J., Bednara M.:
Generation of Distributed Loop Control
In: E. Deprettere, J. Teich, and S. Vassiliadis (ed.): Embedded Processor Design Challenges, Lecture Notes in Computer Science (LNCS), Berlin, Germany: Springer, 2002, p. 154-170
BibTeX: Download - Bednara M., Hannig F., Teich J.:
Boundary control: A new distributed control architecture for space-time transformed (VLSI) processor arrays
35th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA)
In: Matthews M.B. (ed.): Proc. 35th IEEE Asilomar Conf. on Signals, Systems and Computers 2001
URL: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0035573058&origin=inward
BibTeX: Download - Hannig F., Teich J.:
Design Space Exploration for Massively Parallel Processor Arrays
Sixth International Conference on Parallel Computing Technologies (PaCT-2001) (Novosibirsk, 3. September 2001 - 7. September 2001)
In: Proc. of the Sixth International Conference on Parallel Computing Technologies (PaCT-2001) 2001
BibTeX: Download - Teich J., Bednara M.:
Synthesis of FPGA Implementations from Loop Algorithms
First International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA01), (Las Vegas, Nevada, 25. June 2001 - 28. June 2001)
In: Proc. of the First International Conference on Engineering of Reconfigurable Systems and Algorithms 2001
BibTeX: Download - Bednara M., Beyer O., Teich J., Wanka R.:
Hardware-Supported Sorting: Design and Tradeoff Analysis
Workshop on System Design Automation - SDA 2000 (Rathen)
In: Workshop on System Design Automation - SDA 2000 2000
BibTeX: Download - Bednara M., Beyer O., Teich J., Wanka R.:
Hardware Supported Sorting: Design and Tradeoff Analysis
In: In System Design Automation, Kluwer Academic Publishers, 2001, p. 97-107
BibTeX: Download - Bednara M., Hardt W., Rettberg A., Teich J.:
Automated Design Space Exploration on System Level for Embedded Systems
Ninth Annual International HDL Conference and Exhibition (HDL Conf. 2000), (San Jose, CA)
In: Proc. Ninth Annual International HDL Conference and Exhibition 2000
BibTeX: Download - Wolfram Hardt, Franz Rammig, Carsten Böke, Joachim Stroop, Achim Rettberg, Del Castillo, Bernd Kleinjohann, Jürgen Teich:
IP-based System Design within the PARADISE Design Environment
In: Journal of Systems Architecture (2000)
ISSN: 1383-7621
BibTeX: Download - Bhattacharyya SS., Teich J., Zitzler E.:
Optimizing the Efficiency of Parameterized Local Search within Global Search
Int. Conf. on Evolutionary Computation, (La Jolla, CA)
In: Proc. of CEC'2000, the Int. Conf. on Evolutionary Computation 2000
BibTeX: Download - Bednara M., Beyer O., Teich J., Wanka R.:
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, (Boston, MA, 10. July 2000 - 12. July 2000)
In: Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors, pp. 299-308, Boston, MA, U.S.A. IEEE Computer Society Press, July 2000Proc. ASAP'00, the Int. Conf. on Application Specific Systems, Architectures, and Processors 2000
BibTeX: Download - Cieslok F., Esau H., Teich J.:
EXPLORA - Generic Design Space Exploration During Embedded System Synthesis
Int. IFIP Workshop on Distributed and Parallel Embedded Systems, (Schloss Eringerfeld)
In: Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems 2000
BibTeX: Download - Bhadouria VS., Tanase AP., Schmid M., Hannig F., Teich J., Ghoshal D.:
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
In: Journal of Signal Processing Systems 89 (2016), p. 225-242
ISSN: 1939-8018
DOI: 10.1007/s11265-016-1187-5
BibTeX: Download - Tanase AP., Witterauf M., Teich J., Hannig F.:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays
In: ACM Transactions on Embedded Computing Systems 17 (2017), p. 31:1-31:27
ISSN: 1539-9087
DOI: 10.1145/3092952
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