Jorge A. Echavarria Gutiérrez › Department of Computer Science 12

Jorge A. Echavarria, M. Sc.

Jorge Echavarria

since 2015	Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg
2013 − 2014	Exchange Student, Universitat Politècnica de València, Spain
2012 − 2014	M. Sc. Computer Science, National Institute of Astrophysics, Optics and Electronics, Mexico
2005 − 2010	B. Sc. Computer Science, Meritorious Autonomous University of Puebla, Mexico

SS 2019	Approximate Computing
WS 2018/2019	Reconfigurable Computing Seminar: Reliability Analysis in Embedded Systems
WS 2017/2018	Reconfigurable Computing
WS 2016/2017	Reconfigurable Computing
WS 2015/2016	Electronics of Programmable Digital Systems

Analysis and Implementation of an Approximate Kogge-Stone Adder on FPGA
On Switching Activity Minimization Using Approximate Computing Techniques to Reduce Dynamic Power Consumption in FPGAs

Echavarria Gutiérrez JA., Morales-Reyes A., Cumplido R., Salido MÁ., Feregrino C.:
IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms
In: Engineering Applications of Artificial Intelligence (2019)
ISSN: 0952-1976
BibTeX: Download

Echavarria Gutiérrez JA., Schütz K., Becher A., Wildermann S., Teich J.:
Can Approximate Computing Reduce Power Consumption on FPGAs?
25th IEEE International Conference on Electronics Circuits and Systems (Bordeaux, 9. December 2018 - 12. December 2018)
BibTeX: Download
Echavarria Gutiérrez JA., Schütz K., Becher A., Wildermann S., Teich J.:
Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
AxC18: 3rd Workshop on Approximate Computing (Swissôtel Bremen, 31. May 2018 - 1. June 2018)
BibTeX: Download
Echavarria Gutiérrez JA., Wildermann S., Teich J.:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
International Conference on Field Programmable Technology (FPT 2018) (Naha, Okinawa, 10. December 2018 - 14. December 2018)
BibTeX: Download
Echavarria Gutiérrez JA., Wildermann S., Teich J.:
Design Space Exploration of Multi-output Logic Function Approximations
International Conference On Computer Aided Design (ICCAD 2018) (San Diego, CA, 5. November 2018 - 8. November 2018)
DOI: 10.1145/3240765.3240795
BibTeX: Download

Becher A., Echavarria Gutiérrez JA., Ziener D., Wildermann S., Teich J.:
A LUT-Based Approximate Adder
24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016). (Washington DC, 1. May 2016 - 3. May 2016)
DOI: 10.1109/FCCM.2016.16
BibTeX: Download
Echavarria Gutiérrez JA., Wildermann S., Becher A., Teich J., Ziener D.:
FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
International Conference on Field Programmable Technology (FPT 2016) (Xi'an, 7. December 2016 - 9. December 2016)
DOI: 10.1109/FPT.2016.7929536
BibTeX: Download

Echavarria Gutiérrez JA., Morales-Reyes A., Cumplido R., Salido MA.:
FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (Cancun, 8. December 2014 - 10. December 2014)
DOI: 10.1109/ReConFig.2014.7032525
BibTeX: Download

Talk: Can Approximate Computing Reduce Power Consumption on FPGAs?
25th IEEE International Conference on Electronics Circuits and Systems, (ICECS), Bordeaux, France, December 09-12, 2018.

Poster: AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
International Conference on Field Programmable Technology, (FPT), Naha, Okinawa, Japan, December 10-14, 2018.
Talk: Design Space Exploration of Multi-output Logic Function Approximations
International Conference On Computer Aided Design, (ICCAD), San Diego, CA, USA, November 05-08, 2018.

Talk: Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
Workshop on Approximate Computing, (AxC), Bremen, Germany, May 31 – June 01, 2018.

Poster: FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
International Conference on Field Programmable Technology, (FPT), Xi’an, China, December 07-09, 2016.
Poster: A LUT-Based Approximate Adder
24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, USA, May 01-03, 2016.

Talk: Approximate Adder Structures on FPGAs
Workshop on Approximate Computing, (AxC), Paderborn, Germany, October 15-16, 2015.

Poster: FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 08-10, 2014.