Jorge Alfonso Echavarria Gutiérrez
Jorge A. Echavarria, M. Sc.
Curriculum Vitæ
since 2015 | Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design), Friedrich-Alexander University Erlangen-Nürnberg |
2013 − 2014 | Exchange Student, Universitat Politècnica de València, Spain |
2012 − 2014 | M. Sc. Computer Science, National Institute of Astrophysics, Optics and Electronics, Mexico |
2005 − 2010 | B. Sc. Computer Science, Meritorious Autonomous University of Puebla, Mexico |
Research Projects
Research Interests
- Embedded Systems
- Reconfigurable Architectures
- Approximate Computing
Other Interests
- IP Core Watermarking
Teaching
WS 2021/2022 | |
SS 2021 | |
WS 2020/2021 | |
SS 2020 | |
WS 2019/2020 | |
SS 2019 | |
WS 2018/2019 | |
WS 2017/2018 | |
WS 2016/2017 | |
WS 2015/2016 |
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Supervised Theses
- Analysis and Implementation of an Approximate Kogge-Stone Adder on FPGA
- On Switching Activity Minimization Using Approximate Computing Techniques to Reduce Dynamic Power Consumption in FPGAs
Publications
2022
Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
In: it - Information Technology (2022)
ISSN: 1611-2776
DOI: 10.1515/itit-2021-0040
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2021
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*
IEEE European Test Symposium (ETS) (, 24. May 2021 - 28. May 2021)
In: Proceedings of the 26th IEEE European Test Symposium (ETS) 2021
DOI: 10.1109/ETS50041.2021.9465409
BibTeX: Download
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On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
(2021)
URL: http://arxiv.org/abs/2105.05588
BibTeX: Download
(online publication)
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Approximate Logic Synthesis of Very Large Boolean Networks
Design, Automation and Test in Europe, DATE 2021, February 1-5, 2021 (Alpexpo, Grenoble, 1. February 2021 - 5. February 2021)
In: Design, Automation and Test in Europe, DATE 2021 2021
BibTeX: Download
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Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
2021 International Conference On Computer Aided Design (Virtual conference, 1. November 2021 - 4. November 2021)
In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2021 2021
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2020
Probabilistic Error Propagation through Approximated Boolean Networks
57th Annual Design Automation Conference (DAC) (San Francisco, CA, 19. July 2020 - 23. July 2020)
In: Proceedings of the 57th Annual Design Automation Conference 2020
BibTeX: Download
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An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy
AxC20: 5th Workshop on Approximate Computing (San Francisco, CA, 19. July 2020 - 24. July 2020)
BibTeX: Download
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Design Space Exploration of an Approximation-Based Fully Reliable TMR Alternative
8th Prague Embedded Systems Workshop (Horoměřice, 6. November 2020 - 7. November 2020)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Design_Space_Exploration_of_an_Approximation-Based_Fully_Reliable_TMR_Alternative.pdf
BibTeX: Download
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2019
IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms
In: Engineering Applications of Artificial Intelligence (2019)
ISSN: 0952-1976
BibTeX: Download
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2018
Can Approximate Computing Reduce Power Consumption on FPGAs?
25th IEEE International Conference on Electronics Circuits and Systems (Bordeaux, 9. December 2018 - 12. December 2018)
In: Proceedings of IEEE International Conference on Electronics Circuits and Systems 2018
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Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
AxC18: 3rd Workshop on Approximate Computing (Swissôtel Bremen, 31. May 2018 - 1. June 2018)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Evaluation_of_Approximate_Computing_Techniques_for_Power_Reduction_on_FPGAs.pdf
BibTeX: Download
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AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
International Conference on Field Programmable Technology (FPT 2018) (Naha, Okinawa, 10. December 2018 - 14. December 2018)
In: Proceedings of 2018 International Conference on Field Programmable Technology 2018
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Design Space Exploration of Multi-output Logic Function Approximations
International Conference On Computer Aided Design (ICCAD 2018) (San Diego, CA, 5. November 2018 - 8. November 2018)
In: Proceedings of the International Conference On Computer Aided Design 2018
DOI: 10.1145/3240765.3240795
BibTeX: Download
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2017
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders
In: IEEE Embedded Systems Letters (2017), Article No.: 99
ISSN: 1943-0663
DOI: 10.1109/LES.2017.2760922
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Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics
20th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (Sankt Goar, 12. June 2017 - 13. June 2017)
In: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems 2017
DOI: 10.1145/3078659.3078669
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2016
A LUT-Based Approximate Adder
24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016). (Washington DC, 1. May 2016 - 3. May 2016)
In: Proceedings of the 24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines 2016
DOI: 10.1109/FCCM.2016.16
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FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
International Conference on Field Programmable Technology (FPT 2016) (Xi'an, 7. December 2016 - 9. December 2016)
In: Proceedings of 2016 International Conference on Field Programmable Technology 2016
DOI: 10.1109/FPT.2016.7929536
BibTeX: Download
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2015
- Becher A, Echavarria Jorge, Ziener D, Teich J:
Approximate Adder Structures on FPGAs
AxC15: 1st Workshop on Approximate Computing (Paderborn, Germany)
Open Access: https://www12.cs.fau.de/downloads/echavarria/pub/Approximate_Adder_Structures_on_FPGAs.pdf
BibTeX: Download
2014
FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (Cancun, 8. December 2014 - 10. December 2014)
In: Proceedings of 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2014
DOI: 10.1109/ReConFig.2014.7032525
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Misc.
2021
- Online Talk: Approximate Logic Synthesis of Very Large Boolean Networks
Design, Automation and Test in Europe, (DATE), Alpexpo, Grenoble, France, February 1-5, 2021.
2020
- Online Talk: Probabilistic Error Propagation through Approximated Boolean Networks
57th Annual Design Automation Conference, (DAC), San Francisco, CA, USA, July 19-23, 2020. - Online Talk: An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy
Workshop on Approximate Computing, (AxC), San Francisco, CA, USA, July 19-23, 2020.
2018
- Talk: Can Approximate Computing Reduce Power Consumption on FPGAs?
25th IEEE International Conference on Electronics Circuits and Systems, (ICECS), Bordeaux, France, December 09-12, 2018.
- Poster: AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
International Conference on Field-Programmable Technology, (FPT), Naha, Okinawa, Japan, December 10-14, 2018. - Talk: Design Space Exploration of Multi-output Logic Function Approximations
International Conference On Computer-Aided Design, (ICCAD), San Diego, CA, USA, November 05-08, 2018.
- Talk: Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
Workshop on Approximate Computing, (AxC), Bremen, Germany, May 31 – June 01, 2018.
2016
- Poster: FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs
International Conference on Field-Programmable Technology, (FPT), Xi’an, China, December 07-09, 2016. - Poster: A LUT-Based Approximate Adder
24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, USA, May 01-03, 2016.
2015
- Talk: Approximate Adder Structures on FPGAs
Workshop on Approximate Computing, (AxC), Paderborn, Germany, October 15-16, 2015.
2014
- Poster: FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms
International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 08-10, 2014. - Talk: IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms
Segundo Seminario Nacional de Aprendizaje e Inteligencia Computacional, Puebla, Mexico, November 19-21, 2014.
Reviewing − Journals
- JSA — Journal of Systems Architecture
- ACM (TRETS) — Transactions on Reconfigurable Technology and Systems
- IEEE Access — IEEE Access – The Multidisciplinary Open Access Journal
- Microelectronics Reliability — Elsevier – Microelectronics Reliability
- TODAES — Transactions on Design Automation of Electronic Systems